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cynse70256 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-02035 rev. *e revised december 12, 2003 cynse70256 network search engine
cynse70256 document #: 38-02035 rev. *e page 2 of 109 contents 1.0 overview .................................................................................................................. .................... 8 2.0 features .................................................................................................................. .................... 8 3.0 functional description .................................................................................................... ..... 9 3.1 command bus and dq bus .................................................................................................... ......... 9 3.2 database entry (data and mask arrays) ..................................................................................... ..... 9 3.3 arbitration logic ......................................................................................................... ..................... 10 3.4 pipeline and sram control ................................................................................................. ........... 10 3.5 full logic ................................................................................................................ ........................ 10 4.0 signal descriptions ....................................................................................................... ....... 10 5.0 clocks .................................................................................................................... ..................... 12 6.0 phase-lock loop usage ..................................................................................................... .. 13 7.0 registers ................................................................................................................. .................. 13 7.1 comparand registers ....................................................................................................... .............. 13 7.2 mask registers ............................................................................................................ ................... 14 7.3 search successful registers (ssr[0:7]) .................................................................................... .... 14 7.4 command register .......................................................................................................... ............... 15 7.5 information register ...................................................................................................... ................. 16 7.6 read burst address register ............................................................................................... .......... 16 7.7 write burst address register description .................................................................................. .... 17 7.8 nfa register .............................................................................................................. .................... 17 8.0 nse architecture and operatio n overview ..... ........................................... ............... 17 9.0 data and mask addressing ............................ .......................................... .......................... 19 10.0 commands .................. ............................... ................................ ................................ ............... 19 10.1 command codes ............................................................................................................ .............. 19 10.2 commands and command parameters ....................................................................................... 19 10.3 read command ............................................................................................................. ............... 20 10.4 write command ............................................................................................................ ................ 22 10.5 parallel write ........................................................................................................... ..................... 24 10.6 search command ........................................................................................................... .............. 25 10.7 lram and ldev description ................................................................................................ ....... 82 10.8 learn command ............................................................................................................ ............... 82 11.0 depth cascading .......................................................................................................... ......... 84 11.1 depth cascading up to four devices (one block) ....................................................................... 84 11.2 depth cascading up to fifteen devices (four blocks) ................................................................. 84 11.3 depth cascading for a full signal ........................................................................................ ..... 85 12.0 sram addressing ................................... ........................................... ............................ ........ 86 12.1 sram pio access .......................................................................................................... .............. 86 12.2 sram read with a table of up to four devices .......................................................................... 87 12.3 sram read with a table of up to fifteen devices ....................................................................... 89 12.4 sram write with a table of up to four devices .......................................................................... 90 12.5 sram write with table(s) consisting of up to fifteen devices .................................................... 92
cynse70256 document #: 38-02035 rev. *e page 3 of 109 contents (continued) 13.0 power .................................................................................................................... .................... 94 13.1 power-up sequence ........................................................................................................ ............. 94 13.2 power consumption ........................................................................................................ ............. 95 14.0 application .............................................................................................................. ............... 95 15.0 jtag (1149.1) testing .................................................................................................... ......... 96 16.0 electrical specificat ions ...................................... ................................ .......................... 97 17.0 ac timing waveforms ...................................................................................................... .... 98 18.0 pinout descriptions and p ackage diagrams ................................. ........................ 102 19.0 ordering information ..................................................................................................... . 107 20.0 package diagram .......................................................................................................... ...... 107
cynse70256 document #: 38-02035 rev. *e page 4 of 109 list of figures figure 2-1. cynse70256 block diagram........................................................................................... ..... 9 figure 5-1. cynse70256 clocks (clk2x and phs_l) ........................................................................ 12 figure 5-2. cynse70256 clocks (clk1x) .......................................................................................... .12 figure 5-3. cynse70256 clocks for all timing diagrams .................................................................... 13 figure 7-1. comparand register selection during search and learn instructions ............................... 14 figure 7-2. addressing the gmr array ........................................................................................... ...... 14 figure 8-1. cynse70256 database width configuration for each of the two banks .......................... 17 figure 8-2. multiwidth database configurations example ..................................................................... 18 figure 9-1. addressing the cynse70256 data and mask arrays ........................................................ 19 figure 10-1. single-location read cycle timing ................................................................................. .21 figure 10-2. burst read of the data and mask arrays (blen = 4) ....................................................... 22 figure 10-3. single write cycle timing ......................................................................................... ........ 23 figure 10-4. burst write of the data and mask arrays (blen = 4) ................................................... 24 figure 10-5. hardware diagram for a table with four devices ............................................................ 25 figure 10-6. timing diagram for 72-bit search device number 0......................................................... 26 figure 10-7. timing diagram for 72-bit search device number 1......................................................... 27 figure 10-8. timing diagram for 72-bit search device number 3 (last device) .................................. 28 figure 10-9. 72 table with four devices............................................................................................. 29 figure 10-10. hardware diagram for a table with fifteen devices ....................................................... 30 figure 10-11. hardware diagram for a block of up to four devices ..................................................... 31 figure 10-12. timing diagram for each device in block number 0 (miss on each device) ................. 31 figure 10-13. timing diagram for each device a bove the winning device in block number 1 ........... 32 figure 10-14. timing diagram for globally winning device in block number 1 ................................... 33 figure 10-15. timing diagram for devices below th e winning device in block number 1 ................... 34 figure 10-16. timing diagram for devices above t he winning device in block number 2 .................. 35 figure 10-17. timing diagram for globally winning device in block number 2 ................................... 36 figure 10-18. timing diagram for devices below th e winning device in block number 2 ................... 37 figure 10-19. timing diagram for devices above t he winning device in block number 3 .................. 38 figure 10-20. timing diagram for globally winning device in block number 3 ................................... 39 figure 10-21. timing diagram for devices belo w the winning device in block number 3 (except the last device [device 14])........................................................................................... .......... 40 figure 10-22. timing diagra m for device number 3 in block number 3 (device 14 in depth-cascaded table) .................................................................... 41 figure 10-23. 72 table with fifteen devices ....................................................................................... 42 figure 10-24. hardware diagram for a table with four devices .......................................................... 43 figure 10-25. timing diagram for 144-bit search device number 0..................................................... 44 figure 10-26. timing diagram for 144-bit search device number 1..................................................... 45 figure 10-27. timing diagram for 144-bit search device number 7 (last device) .............................. 46 figure 10-28. 144 table with four devices......................................................................................... 47 figure 10-29. hardware diagram for a table with fifteen devices ....................................................... 49 figure 10-30. hardware diagram for a table with four devices .......................................................... 49 figure 10-31. timing diagram for each device in block number 0 (miss on each device) ................. 50 figure 10-32. timing diagram for each device a bove the winning device in block number 1 ........... 51 figure 10-33. timing diagram for globally winning device in block number 1 ................................... 52 figure 10-34. timing diagram for devices below th e winning device in block number 1 ................... 53 figure 10-35. timing diagram for devices above t he winning device in block number 2 .................. 54 figure 10-36. timing diagram for globally winning device in block number 2 ................................... 55 figure 10-37. timing diagram for devices below th e winning device in block number 2 ................... 56 figure 10-38. timing diagram for devices above t he winning device in block number 3 .................. 57
cynse70256 document #: 38-02035 rev. *e page 5 of 109 list of figures (continued) figure 10-39. timing diagram for globally winning device in block number 3 ................................... 58 figure 10-40. timing diagram for devices belo w the winning device in block number 3 except device 14 (the last device)............................................................................................. .......... 59 figure 10-41. timing diagra m for device number 2 in block number 3 (device 14 in a depth-cascaded table) ................................................................. 60 figure 10-42. 144 table with fifteen devices ..................................................................................... 61 figure 10-43. hardware diagram for a table with four devices .......................................................... 62 figure 10-44. timing diagram for 288-bit search device number 0..................................................... 63 figure 10-45. timing diagram for 288-bit search device number 1..................................................... 64 figure 10-46. timing diagram for 288-bit search device number 3 (last device) .............................. 65 figure 10-47. 288 table with four devices......................................................................................... 66 figure 10-48. hardware diagram for a table with fifteen devices ....................................................... 67 figure 10-49. hardware diagram for a block of up to four devices ..................................................... 68 figure 10-50. timing diagram for each device in block number 0 (miss on each device) ................. 69 figure 10-51. timing diagram for each device a bove the winning device in block number 1 ........... 70 figure 10-52. timing diagram for globally winning device in block number 1 ................................... 71 figure 10-53. timing diagram for devices below th e winning device in block number 1 ................... 72 figure 10-54. timing diagram for devices above t he winning device in block number 2 .................. 73 figure 10-55. timing diagram for globally winning device in block number 2 ................................... 74 figure 10-56. timing diagram for devices below th e winning device in block number 2 ................... 75 figure 10-57. timing diagram for devices above t he winning device in block number 3 .................. 76 figure 10-58. timing diagram for globally winning device in block number 3 ................................... 77 figure 10-59. timing diagram for devices belo w the winning device in block number 3 except device 14 (last device)................................................................................................. ............ 78 figure 10-60. timing diagram of the last device in block number 3 (device 14 in the table)............ 79 figure 10-61. 288 table with fifteen devices ..................................................................................... 80 figure 10-62. timing diagram for mixed search (one device)............................................................. 81 figure 10-63. multiwidth configurations example ................................................................................ .81 figure 10-64. timing diagram of learn (except on the last device [tlsz = 01])................................ 83 figure 10-65. timing diagram of learn on device number 3 (tlsz = 01)........................................... 83 figure 11-1. hardware diagram for a block of up to four devices ....................................................... 84 figure 11-2. depth cascading four blocks ....................................................................................... ..... 85 figure 11-3. full signal generation in a cascaded table.................................................................. 86 figure 12-1. hardware diagram of a bl ock of four devices ................................................................. 87 figure 12-2. sram read through device number 0 in a block of four devices ................................ 88 figure 12-3. sram read timing for device num ber 7 in a block of four devices .............................. 88 figure 12-4. hardware diagram of fifteen devices using four blocks ................................................ 89 figure 12-5. sram read through device nu mber 0 in a bank of fifteen devices (device number 0 timing)....................................................................................................... .............. 90 figure 12-6. sram read through device nu mber 0 in a bank of fifteen devices (device number 14 timing)...................................................................................................... ............. 90 figure 12-7. hardware diagram of a bl ock of four devices ................................................................. 91 figure 12-8. sram write through device number 0 in a block of four devices................................. 91 figure 12-9. sram write timing for device number 3 in block of four devices ................................. 92 figure 12-10. table of fifteen devices (four blocks) ........................................................................... 93 figure 12-11. sram write through device number 0 in bank of fifteen devices (device 0 timing)................................................................................... ..... 93 figure 12-12. sram write through device number 0 in bank of fifteen cynse70256 devices (d evice number 14 timing)................................................. 94
cynse70256 document #: 38-02035 rev. *e page 6 of 109 list of figures (continued) figure 13-1. power-up sequence (clk2x) ......................................................................................... .. 95 figure 13-2. power consumption of cynse70256............................................................................... 95 figure 14-1. sample switch/router using the cynse70256 device ................................................... 96 figure 17-1. input wave form for cynse70256 .................................................................................. 99 figure 17-2. output load for cynse70256 ........................................................................................ .. 99 figure 17-3. 2.5 i/o output load equivalent for cynse70256 ............................................................ 99 figure 17-4. ac timing wave forms with clk2x .............................................................................. 100 figure 17-5. ac timing wave forms with clk1x .............................................................................. 101 figure 18-1. pinout diagram.................................................................................................... ............ 102
cynse70256 document #: 38-02035 rev. *e page 7 of 109 list of tables table 4-1. cynse70256 signal description ...................................................................................... .. 10 table 7-1. register overview (bank0 and bank1) ............................................................................... 1 3 table 7-2. search successful register description ............................................................................. 15 table 7-3. command register description ....................................................................................... .... 15 table 7-4. information register description ................................................................................... ...... 16 table 7-5. read burst register description .................................................................................... ..... 16 table 7-6. write burst register description ................................................................................... ...... 17 table 7-7. nfa register ....................................................................................................... ................ 17 table 8-1. bit position match ................................................................................................. ............... 18 table 10-1. command codes ..................................................................................................... .......... 19 table 10-2. command parameters ................................................................................................ ...... 20 table 10-3. read command parameters ........................................................................................... .. 20 table 10-4. read address format for data array, mask array, or sram ........................................... 21 table 10-5. read address format for internal registers ..................................................................... 22 table 10-6. read address format for data and mask arrays .............................................................. 22 table 10-7. write address format for data array, mask array, or sram (single write) ..................... 23 table 10-8. write address format for internal registers ..................................................................... 23 table 10-9. write address format for data and mask array (burst write) .......................................... 24 table 10-10. hit/miss assumptions ............................................................................................. ......... 25 table 10-11. search latency from instruct ion to sram access cycle ................................................ 29 table 10-12. shift of ssf and ssv from sadr ............... .......................................... .......................... 29 table 10-13. hit/miss assumptions ............................................................................................. ......... 30 table 10-14. search latency from instruct ion to sram access cycle ................................................ 42 table 10-15. shift of ssf and ssv from sadr ............... .......................................... .......................... 42 table 10-16. hit/miss assumptions ............................................................................................. ......... 43 table 10-17. search latency from instruct ion to sram access cycle ................................................ 47 table 10-18. shift of ssf and ssv from sadr ............... .......................................... .......................... 47 table 10-19. hit/miss assumptions ............................................................................................. ......... 48 table 10-20. search latency from instruct ion to sram access cycle ................................................ 61 table 10-21. shift of ssf and ssv from sadr ............... .......................................... .......................... 61 table 10-22. hit/miss assumptions ............................................................................................. ......... 62 table 10-23. search latency from instruct ion to sram access cycle ................................................ 66 table 10-24. shift of ssf and ssv from sadr ............... .......................................... .......................... 66 table 10-25. hit/miss assumptions ............................................................................................. ......... 67 table 10-26. search latency from instruct ion to sram access cycle ................................................ 80 table 10-27. shift of ssf and ssv from sadr ............... .......................................... .......................... 80 table 10-28. searches with cfg_l set high ..................................................................................... 82 table 10-29. sram write cycle latency from second cycle of learn instruction .............................. 83 table 12-1. sram bus address .................................................................................................. ......... 86 table 15-1. supported operations .............................................................................................. ......... 96 table 15-2. tap device id register ............................................................................................ ......... 96 table 16-1. dc electrical characteri stics for cynse70256 ................................................................ 97 table 16-2. operating conditions for cynse70256 ............................................................................ 97 table 17-1. ac timing parameters with clk2x .................................................................................. 9 8 table 17-2. ac timing parameters with clk1x .................................................................................. 9 8 table 17-3. ac table for test condition of cynse70256 ................................................................... 99 table 18-1. pinout descriptions for pinout diagram ........................................................................... 1 02 table 19-1. ordering information .............................................................................................. .......... 107
cynse70256 document #: 38-02035 rev. *e page 8 of 109 1.0 overview cypress semiconductor corporation?s (cypress?s) cynse70256 network search engine (nse) incorporates patent-pending associative processing technology? (apt) and is designed to be a high-performance, pipelined, synchronous, 256k-entry nse. the cynse70256 database entry size can be 72 bits, 144 bits, or 288 bits. in the 72-bit entry m ode, the size of the database is 128k entries. in the 144-bit mode, the size of the database is 64k entries, and in the 288-bit mo de, the size of the database i s 32k entries. the cynse70256 is configurable to support multiple databases with different entry sizes. the 36-bit entry table ca n be implemented using the global mask regi sters (gmrs), building database size of 256k entries with a single device. the nse can sustain 83 million transactions per second when the database is programmed or configured as 72 or 144 bits. when the database is programmed to have an entry size of 36 or 288 bits, the nse will perform at 41.5 million transactions per secon d. cypress?s cynse70256 can be used to accelerate network prot ocols such as longest-prefix match (cidr), arp, mpls, and other layer 2, 3, and 4 protocols. this high-speed, high-capacity nse can be deployed in a variet y of networking and communicat ions applications. the perfor- mance and features of t he cynse70256 make it attractive in applications su ch as enterprise lan switches and routers, and broadband switching and/or routing equipment that supports mult iple data rates at oc?48 and beyond. the nse is designed to be scalable in order to support network database sizes of up to 3 840k entries specifically for en vironments that require large network policy databases. figure 2-1 on page 9 shows the block diagram for the cynse70256 device. 2.0 features ? 256k 36-bit entries in a single device ? 128k entries in 72-bit mode, 64k entries in 144-bit mode, 32k entries in 288-bit mode ? 83 million transactions per second in 72- and 144-bit configurations (cfgs) ? 41.5 million transactions in 36- and 288-bit configurations ? searches any subfield in a single cycle ? synchronous pipelined operation ? up to fifteen nses can be cascaded ? when cascaded, database entries can range to 3840k 36-bit entries ? multiple width tables in a single database bank ? glueless interface to industry-standard srams and/or ssrams ? simple hardware instruction interface ? ieee 1149.1 test access port ? 1.5v core voltage supply ? 2.5v/3.3v i/o voltage supply ? 388-pin bga package .
cynse70256 document #: 38-02035 rev. *e page 9 of 109 3.0 functional description the following subsections contain command (cmd) and dq bu s (command and databus), databa se entry, arbitration logic, pipeline and sram control, and full logic descriptions. 3.1 command bus and dq bus cmd[10:0] carries the command and its associat ed parameters. dq[71:0] is used for data transfer to and from the database entries, which comprise data and mask fields that are organized as data and mask arrays. the dq bus carries the search data (of the data and mask arrays and internal registers) during the search command as well as the address and data during read and/or write operations. the dq bus can also carry address informa tion for the transparent acce sses to the external srams and/or ssrams. 3.2 database entry (data and mask arrays) each database entry comprises data and mask fields. the resultan t value of the entry is ?1,? ?0,? or ?x (do not care),? dependi ng on the value in the data mask bit. the on-chip priority encoder se lects the first matching entry in the database that is neares t to location 0. compare/pio data address decode match logic compare/pio data dq[71:0] cmdv cmd[10:0] lhi[6:0] command and pio access priority encode cmd arbitration logic lho[1:0] pipeline and sram control sadr[23:0] oe_l bho[2:0] ssf we_l ce_l id[4:1] bhi[2:0] ssv ack tap tap controller ale_l fulo[1:0] fuli[6:0] eot full logic full rst_l phs_l decode comparand register pairs [15:0] global mask register pairs [15:0] information and command register burst read register burst write register next-free address register search successful index registers [7:0] clk1x/clk2x [all registers are 72-bits wide.] configurable as 128k 72 64k 144 32k 288 mask array 128k 72 64k 144 32k 288 data array clk_mode bank 0 bank 1 configurable as block diagram figure 2-1. cynse70256 block diagram
cynse70256 document #: 38-02035 rev. *e page 10 of 109 3.3 arbitration logic when multiple nses are cascaded to create large databases, the data being searched is presented to all nses simultaneously in the cascaded system. if multiple matches occur, arbitration logic on the nses will enable the winning device (the one with a matching entry closest to address 0 of the cascaded database) to drive the sram bus. 3.4 pipeline and sram control pipeline latency is added to give enough time to a cascaded system?s arbitration logic to determine the devic e that will drive the index of the matching entry on the sr am bus. pipeline logi c adds latency to bo th the sram access cycles and the search successful flag (ssf) and search successful fl ag valid (ssv) signals to align them to the host asic receiving the associated da ta. 3.5 full logic bit[0] in each of the 72-bit entries has a special purpose for the learn command (0 = empty, 1 = full). when all the data entri es have bit[0] set to 1, the database asse rts the full flag, indicating that all the nses in the depth-cascaded array are full. 4.0 signal descriptions table 4-1 lists and describes all cynse70256 signals. table 4-1. cynse70 256 signal description pin name pin type [1] pin description clocks and reset clk_mode i clock mode . this signal allows the selection of cl ock input to the clk1x/clk2x pin. if the clk_mode pin is low, clk2x must be su pplied on that pin. phs_l must also be supplied. if the clk_mode pin is high, clk1x must be supplied on the clk2x/clk1x pin, and the phs_l signal is not required. when the clk_mode is high, phs_l is unused and should be externally grounded. clk2x/clk1x i master clock . depending on the clk_mode pin, either the clk2x or the clk1x must be supplied. cynse70256 samples control and data signals on both edges of clk1x (if clk1x is supplied). cynse70256 samples all data and control pins on the positive edge of clk2x (if the clk2x and phs_l signals are supplied). all signals are driven out of the device on the rising edge of clk1x (if clk1x is supplied), and are driven on the rising edge of clk2x when phs_l is low (if clk2x is supplied). phs_l i phase . this signal runs at half the frequency of clk2x and generates an internal clk from clk2x. see section 5.0, ?clocks,? on page 12. rst_l i reset . driving rst_l low initializes the device to a known state. cfg_l i configuration . when cfg_l is low, cynse70256 will operate in backward compatibility mode with cynse70032 and cynse70064. when cfg_l is low, the cmd[10:9] should be externally grounded. with cfg_l low, the device will behave identically with cynse70032 and cynse70064, and the new feature added to cynse70256 will be disabled. when cfg_l is high, the addition al cmd[10:9] can be used and the following additional features will be supported: 1. sixt een pairs of global masks are supported instead of eight; 2. parallel write to the data and mask arrays is supported (see subsection 10.5, ?parallel write,? on page 24) ; and 3. configuring tables of up to three different widths does not require table identification bits in the data array, thus saving two bits from each 72-bit entry. command and dq bus cmd[10:0] i command bus . [1:0] specifies the command; [10:2] contains the command parameters. the descriptions of individual cmds explains the details of the parameters. the encoding of cmds based on the [1:0] field are: 00: pio read 01: pio write 10: search 11: learn. cmdv i command valid . this signal qualifies the command bus: 0: no command 1: command.
cynse70256 document #: 38-02035 rev. *e page 11 of 109 dq[71:0] i/o address/data bus . this signal carries the read and write address and data during register, data, and mask array operations. it carries the compare data during search operations. it also carries the sram address during sram pio accesses. ack [2] t read acknowledge . this signal indicates that valid data is available on the dq bus during register, data, and mask array read operations, or that the data is available on the sram data bus during sram read operations. eot [2] t end of transfer . this signal indicates the end of burst transfer to the data or mask array during read or write burst operations. ssf t search successful flag . when asserted, this signal indicates that the device is the global winner in a search operation. ssv t search successful flag valid . when asserted, this signal qualifies the ssf signal. high_speed i high speed . this pin must be connected to ground (v ss ). it is provided for backward as well as forward device compatibility. sram interface sadr[23:0] t sram address . this bus contains address lines to access off-chip srams that contain associative data. see table 12-1 for the details of the ge nerated sram address. in a database of multiple cynse70256s, each corresponding sadr bit from all cascaded devices must be connected. ce_l t sram chip enable . this is the chip-enable (ce) control for external srams. in a database of multiple cynse70256s, ce_l of all cascaded devices must be connected. this signal is then driven by only one of the devices. we_l t sram write enable . this is the write-enable control for external srams. in a database of multiple cynse70256s, we_l of all cascad ed devices must be connected. this signal is then driven by only one of the devices. oe_l t sram output enable . this is the output-enable (oe) co ntrol for external srams. only the last device drives this signal (with the lram bit set). ale_l t address latch enable . when this signal is low, the addresses are valid on the sram address bus. in a database of multiple cyn se70256s, the ale_l of all cascaded devices must be connected. this signal is th en driven by only one of the devices. cascade interface lhi[6:0] i local hit in . these pins depth-cascade the device to form a larger table. one signal of this bus is connected to the lho[1] or lho[0] of each of the upstream devices in a block. all unused lhi pins are connected to a logic 0. for more informati on, see section 11.0, ?depth cascading,? on page 84. lhi[0] stays unconnected. lho[1:0] o local hit out . the lho[1] and the lho[ 0] are connected to one input on the lhi bus (from up to four downstream devices in a block totalling up to four). for more information, see section 11.0, ?depth cascading,? on page 84. bhi[2:0] i block hit in . inputs from the previous block bho[2:0] are tied to bhi[2:0] of the current device. in a four-block system, the last bloc k can contain only seven devices because the identification code 11111 is used for broadcast access. bho[2:0] o block hit out . these outputs from the last device in a block are connected to the bhi[2:0] inputs of the devices in the downstream blocks. fuli[6:0] i full in . each signal in this bus is connected to fulo[0] or fulo[1] of an upstream device to generate the full flag for the depth-ca scaded block. fuli[0] stays unconnected. fulo[1:0] o full out . both of these signals must be connected to the fuli of up to four downstream devices in a depth-cascaded table. bit[0] in the data array indicates whether the entry is full (1) or empty (0). this signal is asserted if all bits in the data array are 1s. (refer to section 11.0, ?depth cascading,? on page 84, for information on how to generate the full flag.) full o full flag . when asserted, this signal indicates that the table of multiple depth-cascaded devices is full. table 4-1. cynse70 256 signal description (continued) pin name pin type [1] pin description
cynse70256 document #: 38-02035 rev. *e page 12 of 109 5.0 clocks if the clk_mode pin is low, cynse70256 receives the clk2x and phs_l signals. it uses the phs_l signal to divide clk2x and generate an internal clock (clk [3, 4] ), as shown in figure 5-1 . the cynse70256 uses clk2x and clk for internal opera- tions. if the clk_mode pin is high, cynse70256 receives clk1x on ly. cynse70256 uses an internal phase-lock loop (pll) to double the frequency of clk1x and then divides that clock by tw o to generate a clk for internal operations, as shown in figure 5-2 . notes: 1. i = input only, i/o = input or output, o = output only, t = three-state output. 2. ack and eot require a weak external pulldown such as 47k ? or 100k ? . 3. any reference to ?clk? cycl es means one cycle of clk. 4. ?clk? is an internal clock signal. 5. for the purpose of showing timing diagrams, all such diagrams in this document will be shown in clk2x mode. for a timing diag ram in clk1x mode, the following substitution can be made (see figure 5-3 ). device identification id[4:0] i device identificatio n. the binary-encoded device identification (id[4:1]) for a depth-cascaded system starts at 0000 and goes up to 1110. 1111 is reserved for a special broadcast address that selects all cascaded nses in the system. on a broadcast read-only, the device with the ldev bit set to 1 responds. id[0] stays unconnected. supplies v dd n/a chip core supply : 1.5v. v ddq n/a chip i/o supply : 2.5v/3.3v. test access port tdi i test access port?s test data in. tck i test access por t?s test clock. tdo t test access port?s test data out. tms i test access port?s test mode select. trst_l i test access port?s reset. table 4-1. cynse70 256 signal description (continued) pin name pin type [1] pin description clk2x phs_l clk [4] figure 5-1. cynse70256 clocks (clk2x and phs_l) clk1x clk [4] figure 5-2. cynse70256 clocks (clk1x) [5]
cynse70256 document #: 38-02035 rev. *e page 13 of 109 6.0 phase-lock loop usage when the device first powers up, it takes 0. 5 ms to lock the internal pll. during th is pll, the rst_l must be held low for prop er initialization of the device. it also takes 32 extra clk1x cycles in clk1x mode and 64 extra cycles in clk2x mode. setup and hold requirements will change in clk1x mode if the duty cycle of the clk1 x is varied. all signals to the device in clk1x mode are sampled by a clock that is generated by multiplying clk1x by two. since the pll has a locking range, the device will only work between the range of frequencies specified in the timing specific ation section of this datasheet. 7.0 registers all registers in the cynse70256 device are 72 bits wide. the cy nse70256 contains two banks of sixteen pairs of comparand storage registers, sixteen pairs of gmrs, ei ght search successful index r egisters, and one each of co mmand, information, burst read, burst write, and next -free address registers. table 7-1 provides an overview of all the cynse70256 registers. the registers are in ascending address order; each regi ster group is described in the following subsections. 7.1 comparand registers the device contains two banks of 32 72-bit comparand registers (sixteen pairs) dynamically selected in every search operation to store the comparand presented on the dq bus. the learn comm and will later use these registers when it is executed. the cynse70256 device stores the search command?s cycle a co mparand in the even-numbered register and the cycle b comparand in the odd-numbered register, as shown in figure 7-1 for each of the two banks of registers. table 7-1. register overview (bank0 and bank1) address abbreviation type name 0?31 comp0?31 r sixteen pairs of comparand regi sters that store comparands from the dq bus for learning later. 32?47 96?111 masks rw sixteen gmr pairs. 48?55 ssr0?7 r eight search successful index registers. 56 command rw command register. 57 info r information register. 58 rburreg rw burst read register. 59 wburreg rw burst write register. 60 nfa r next-free address register. 61?63 ? ? reserved. clk2x phs_l clk1x use for clk2x mode use for clk1x mode figure 5-3. cynse70256 cloc ks for all timing diagrams
cynse70256 document #: 38-02035 rev. *e page 14 of 109 7.2 mask registers the device contains two banks of 32 72-bit gmrs (sixteen pairs) dynamically selected in every search operation to select the search subfield. the addressing of these registers is explained in figure 7-2 . the 4-bit gmr index supplied on the command bus can apply sixteen pairs of global masks during search and write oper ations, as shown below. [6] each mask bit in the gmrs is used during search and write operations. in search operations, setting the mask bit to 1 enables compares; setting the mask bit to 0 disables compares at the corresponding bit position (forced match). in write operations to the data or mask array, setting the mask bit to 1 enables writes ; setting the mask bit to 0 disables writes at the correspondin g bit position. 7.3 search successful registers (ssr[0:7]) the device contains two banks of eight search successful register s (ssrs) to hold the index of the location at which a successf ul search occurred. the format of each register is described in table 7-2 . the search command specifies which ssr stores the index of a specific search command in cycl e b of the search instructi on. subsequently, the host asic can use this register to access that data array, mask array, or external sram usi ng the index as part of the indirect access address (see table 10-3 and table 10-6 ). the device with a valid bit set performs a read or write operation. all other devi ces suppress the operation. note: 6. in 72-bit search and write operations, the host asic must progr am both the even and odd mask registers with the same values f or each of the banks. 143 0 72 72 1 0 3 2 5 4 7 6 30 31 index 0 15 1 add ress figure 7-1. comparand register selecti on during search and learn instructions 001 123 245 367 489 51011 61213 71415 81617 91819 10 20 21 11 22 23 12 24 25 13 26 27 14 28 29 15 30 31 index 143 72 72 search and write command global mask selection 0 figure 7-2. addressing the gmr array
cynse70256 document #: 38-02035 rev. *e page 15 of 109 7.4 command register table 7-3 describes the command registers? fields fo r each of the two banks; bank 0 and bank 1. table 7-2. search successf ul register description field range initial value description index [15:0] x index . this is the address of the 72-bit entry where a successful search occurs. the device updates this field only when the search is successful. if a hit occurs in a 144-bit entry-size quadrant, the least-significant bit (lsb) is 0. if a hit occurs in a 288-bit en try-size quadrant, the two lsbs are 00. this index updates if the device is either a local or global winner in a search operation. ? [30:16] 0 reserved . valid [31] 0 valid . during search operation in a dep th-cascaded configuration, this ban of the device that is a global winner in a match sets this bit to 1. this bit updates only when the device is a global winner in a search operation. ? [71:32] 0 reserved . table 7-3. command register description field range initial value description srst [0] 0 software reset . if 1, this bit resets the bank with the sa me effect as a hardwa re reset. internally, it generates a reset pulse lasting for eight clk cycles. this bit automatica lly resets to a 0 after the reset has completed. deve [1] 0 device enable . if 0, it keeps the sram bus (sadr, we_l, ce_l, oe_l and ale_l), ssf, and ssv signals in a three-state condition and forces the cascade interface ou tput signals lho[1:0] and bho[2:0] to 0. it also keeps the dq bus in input mode. the purpose of this bit is to make sure that there are no bus contentions w hen the devices power up in the system. tlsz [3:2] 01 table size . the host asic must program this field to configure each bank into a table of a certain size. this field affects the pipeline latency of the search and learn oper ations as well as the read and write accesses to the sram (sadr[ 23:0], ce_l, oe_l, we _l, ale_l, ssv, ssf, and ack). once programmed, the search latency stays constant. latency in number of cl k cycles with high_speed low: 01: up to four devices 5 10: up to fifteen devices 6 11: reserved. hlat [6:4] 000 latency of hit signals . this field adds further latency to the ssf and ssv signals during search, and ack signal during sram read access by the following number of clk cycles. 000: 0 100: 4 001: 1 101: 5 010: 2 110: 6 011: 3 111: 7. ldev [7] 0 last device in the cascade . when set, this is the last bank of the last device in the depth-cascaded table and is the default driver for the ssf and ssv signals. in the event of a search failure, the bank with this device with this bit set drives th e hit signals as follows: ssf = 0, ssv = 1. during non-search cycles, the device with this bit set dr ives the signals as follows: ssf = 0, ssv = 0. lram [8] 0 last device on the sram bus . when set, this is the last bank of the last device on the sram bus in the depth-cascaded table and is the default driver for the sadr, ce_l, we_l, and ale_l signals. in cycles where no cynse70256 dev ice in a depth-cascaded table drives these signals, this drives the signals as follows: sadr = 23?hffffff, ce_l = 1, we_l = 1, and ale_l = 1. oe_l is always driven by the device for which this bit is set.
cynse70256 document #: 38-02035 rev. *e page 16 of 109 7.5 information register table 7-4 describes the information register fields for both banks. 7.6 read burst address register table 7-5 shows the read burst address register (rburreg) fields th at must be programmed before a burst read when a read burst transfer is done from any bank. cfg [24:9] 0000000000 000000 database configuration . the device is divided internally into two banks each consisting of sixteen partitions of 8k 72, each of wh ich can be configured as 8k 72, 4k 144, or 2k 288, as follows. 00: 8k 72 01: 4k 144 10: 2k 288 11: low power, partition not used for search. bits[10:9] apply to configuring the first partition in the address space. bits[12:11] apply to configuring the second partition in the address space. bits[14:13] apply to configuring the third partition in the address space. bits[16:15] apply to configuring the fourth partition in the address space. bits[18:17] apply to configuring the fifth partition in the address space. bits[20:19] apply to configuring the sixth partition in the address space. bits[22:21] apply to configuring the se venth partition in the address space. bits[24:23] apply to configuring the eighth partition in the address space. [71:25] 0 reserved . table 7-4. information register description field range initial value description revision [3:0] 0001 revision number . this is the current de vice revision number. numbers start at one and increment by one for each revision of the device. implementation [6:4] 001 this is the cynse70256 implementation number. reserved [7] 0 reserved . device id [15:8] 00000100 this is the device identification number. mfid [31:16] 1101_1100_0111_ 1111 manufacturer id . this field is the same as the manufacturer identi- fication number and continuation bits in the tap controller. reserved [71:32] reserved . table 7-5. read burst register description field range initial value description adr [15:0] 0 address . this is the starting address of the data or mask array during a burst-read operation from a bank. it automatically increments by one for each successive read of the data or mask array. once the operation is complete, the contents of this field must be reinitialized for the next operation. [18:16] reserved . blen [27:19] 0 length of burst access . the device provides the capability to read from 4?511 locations in a single burst from each bank. the blen decre- ments automatically. once the operation is complete, the contents of this field must be reinitialized for the next operation. [71:28] reserved . table 7-3. command register description (continued) field range initial value description
cynse70256 document #: 38-02035 rev. *e page 17 of 109 7.7 write burst address register description table 7-6 describes the write burst address register (wburreg) fi elds that must be programmed before a burst write. 7.8 nfa register bit[0] of each 72-bit data entry is specially designated for use in the operation of the learn command in each of the banks. fo r 72-bit-configured quadrants, this bit indicates whether a location is full (bit set to 1) or empty (bit set to 0). every write and/or learn command loads the address of the first 72-bit location that contains a 0 in the entry?s bit[0]. this is stored in the nfa register(see table 7-7 ). if all the bits[0] in a device for both the banks within the device are set to 1, the cynse70256 asserts fulo[1:0] to 1. for 144-bit-configured quadrants, the lsb of the nfa register is always set to 0. the host asic must set both bit[0] and bit[72 ] in a 144-bit word to either 0 or 1 to indicate full or empty st atus. both bit[0] and bit[72] must be set to either 0 or 1, (tha t is, the 10 or 01 settings are invalid). 8.0 nse architecture and operation overview the cynse70256 device consists of two banks of 64k 72-bit st orage cells referred to as data bits. there is a mask cell corresponding to each data cell. figure 8-1 shows the three organizations of the devi ce based on the value of the cfg bits in the command register. table 7-6. write burst register description field range initial value description adr [15:0] 0 address . this is the starting address of the data or mask array during a burst-write operation from a bank. it automatically increments by one for each successive write of the data or mask array. once the operation is complete, the contents of this field must be reinitialized for the next operation. [18:16] reserved . blen [27:19] 0 length of burst access . the device provides the capability to write from 4?511 locations in a single burst. the bl en decrements automatically. once the operation is complete, the contents of this field must be reinitialized for the next operation. [71:28] reserved . table 7-7. nfa register address 71?16 15?0 60 reserved index data 32 k 144 data masks 16 k 288 cfg = 0101010101010101 cfg = 1010101010101010 data masks 64 k 72 cfg = 0000000000000000 masks figure 8-1. cynse70256 database width configuration for each of the two banks
cynse70256 document #: 38-02035 rev. *e page 18 of 109 during a search operation, the search data bit (s), data arra y bit (d), mask array bit (m), and global mask bit (g) are used in the following manner to generate a match at that bit position (see table 8-1 ). the entry with a match on every bit position results in a successful search. in order for a successful search within a device to make the device the local winner, all 72-bit positions must generate a matc h for a 72-bit entry in 72-bit-c onfigured quadrants, or all 144-bit positions must generate a match for two consecutive even and o dd 72-bit entries in quadrants configured as 144 bits, or all 288-bit positions must genera te a match for four consecutive entries aligned to four entry-page boundaries of 72-bit entries in quadrants configured as 288 bits. an arbitration mechanism using a cascade bus determines the global winning device among the local winning devices in a search cycle. the global winning device drives the sram bus, the ssv, an d the ssf signals. in case of a search failure, the device(s) with a bank with the ld ev and lram bits set drives the sram bus, ssf, and ssv signals. the cynse70256 device can be configured to contain tabl es of different widths, ev en within the same chip. figure 8-2 shows a sample configuration of different widths. table 8-1. bit position match gmd smatch 0xxx1 10xx1 11001 11100 11010 11111 16k 144 8k 288 32k 72 cfg (bank 0)= 11 11 11 11 00 00 00 00 cfg (bank 1)= 10 10 10 10 01 01 01 01 32k inactive (low power). bank 0 bank 1 figure 8-2. multiwidth database configurations example
cynse70256 document #: 38-02035 rev. *e page 19 of 109 9.0 data and mask addressing figure 9-1 shows cynse70256 data and mask array addressing for both bank 0 and bank 1. 10.0 commands a master device such as an asic controller issues comman ds to the cynse70256 device using the cmdv signal and the command bus. the following subsections de scribe the operation of these commands. 10.1 command codes the cynse70256 device implements four basic commands, as shown in table 10-1 . the command code must be presented to cmd[1:0] while keeping the cmdv signal high for two clk2x cycles (cycles a and b) when the clk_mode pin is low. in clk2x mode, the controller asic must align the instructions us ing the phs_l signal. the command code must be presented to cmd[1:0] while keeping the cmdv signal high for one clk1x cycle when the clk_mode pin is high. in clk1x mode the high phase is cycle a and the lo w phase is cycle b. the cmd[ 10:2] field passes command para meters in cycles a and b. 10.2 commands and co mmand parameters table 10-2 lists the command bus fields that contain the cynse70 256 command parameters and their respective cycles. each command is described separately in the subsections that follow. table 10-1. command codes command code command description 00 read reads one of the following: data array, mask array, device registers, or external sram. 01 write writes one of the following: data array, ma sk array, device registers, or external sram. 10 search searches the data array for a desired patt ern using the specified register from the gmr array and local mask associated with each data cell. 11 learn the device has internal storage for up to sixteen comparands that it can learn. the device controller can insert t hese entries at the next-free address (as specified by the nfa register) using the learn instruction. cfg = 0000000000000000 (bank 0 and bank 1) cfg = 1010101010101010 (bank 0 and bank 1) 71 0 72 0 1 2 3 65535 283 0 72 72 3 2 1 0 7 6 5 4 65532 65533 65534 65535 72 72 cfg = 0101010101010101 (bank 0 and bank 1) 143 0 72 72 1 0 3 2 5 4 7 6 65534 65535 (72-bit configuration) (288-bit configuration) (144-bit configuration) 64k 16k 32k (bank 0) 0 1 2 3 65535 64k (bank 1) 16k 3 2 1 0 7 6 5 4 65532 65533 65534 65535 3 2 5 4 7 6 65534 65535 1 0 32k figure 9-1. addressing the cynse70256 data and mask arrays
cynse70256 document #: 38-02035 rev. *e page 20 of 109 10.3 read command the read can be a single read of a data array, a mask array, an sram, or a register location (cmd[2] = 0). it can be a burst read of the data (cmd[2] = 1) or mask array locations us ing an internal auto-incrementin g address register (rburadr). a description of each type is provided in table 10-3 . a single-location re ad operation lasts six cycles, as shown in figure 10-1 . the burst read adds two cycles for each successive read. t he sadr[23:21] bits supplied in read instruction cycle a drives sadr[23:21] signals during a read of an sram location. notes: 7. use cmd[8:0] only and connect cmd[10:9] to ground with cfg_l low. 8. for a description of cmd[9] and cmd[2], see search 288-bit-c onfigured tables and mixed-size searches with cfg_l high. 9. the 288-bit-configured devices or 288-bi t-configured quadrants within devices do not support the learn instruction. 10. the device registers and external sram can only be read in single-read mode. table 10-2. command parameters cmd [7,8] cyc 10 9 8 7 6 5 4 3 2 1 0 read a x x sadr[23] sadr[22] sadr[21] 0 0 0 0 = single 1 = burst 00 bx x 0 0 0 000 0 = single 1 = burst 00 write a gmr index [9] 0: normal write 1: parallel write sadr[23] sadr[22] sadr[21] gmr index [2:0] 0 = single 1 = burst 01 bgmr index [9] 0: normal write 1: parallel write 000gmr index [2:0] 0 = single 1 = burst 01 search a gmr index [9] 72 bits: 0 144 bits: 1 288 bits: x sadr[23] sadr[22] sadr[21] gmr index [2:0] 72 bits or 144 bits: 0 288 bits: 1 in first cycle 0 in second cycle 10 b x ssr index[2:0] comparand register index 1 0 learn [9] a x x sadr[23] sadr[22] sadr[21] comparand register index 1 1 bx x 0 0 mode 0: 72 bits 1: 144 bits comparand register index 1 1 table 10-3. read command parameters cmd parameter cmd[2] read command description 0 single read reads a single location of the data array, mask array, external sram, or device registers. all access information is applied on the dq bus. 1 burst read reads a block of locations from the data or mask array as a burst. rburadr specifies the starting address and the length of the data transfer from the data or mask array; it also auto-increments the address for each access. all other access information is applied on the dq bus. [10]
cynse70256 document #: 38-02035 rev. *e page 21 of 109 the single read operation takes six clk cycles that operate in the following sequence. ? cycle 1 : the host asic applies the read instruction on cmd[1:0] (cmd[2] = 0) using cmdv = 1, and the dq bus supplies the address, as shown in table 10-4 and table 10-5 . the host asic selects the cynse70256 device for which id[4:1] matches the dq[25:22] lines. the dq[21] specifies the bank of the device. if dq[25:21] = 11111, the host asic selects the cynse 70256 with the ldev bit set. the host asic also supplies sadr[23:21] on cmd[8:6] in cycle a of the read instruction if the read is directed to the external sram. ? cycle 2 : the host asic floats dq[71:0] to a three-state condition. ? cycle 3 : the host asic keeps dq[71:0] in a three-state condition. ? cycle 4 : the selected device starts to drive the dq[71:0] bus and drives the ack signal from z to low. ? cycle 5 : the selected device drives the read data from the addre ssed location on the dq[71:0] bus, and drives the ack signal high. ? cycle 6 : the selected device floats the dq[71:0] to a th ree-state condition and drives the ack signal low. at the termination of cycle 6, th e selected device releases th e ack line to a three-state cond ition. the read instruction is complete, and a new operation can begin. [11] table 10-5 describes the read address format for the internal registers. figure 10-2 illustrates the timing diagram for the burst read of the data or mask array. table 10-4. read address format for data array, mask array, or sram dq [71:30] dq [29] dq [28:26] dq [25:22] dq [21] dq [20:19] dq [18:16] dq [15:0] reserved 0: direct 1: indirect ssr index (applicable if dq[29] is indirect) id bank 0 or 1 00: data array reserved if dq[29] is 0, this field carries the address of the data array location. if dq[29] is 1, the ssr index specified on dq[28:26] is used to generate the address of the data array location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [12] reserved 0: direct 1: indirect ssr index (applicable if dq[29] is indirect) id bank 0 or 1 01: mask array reserved if dq[29] is 0, this field carries the address of the mask array location. if dq[29] is 1, the ssr index specified on dq[28:26] is used to generate the address of the mask array location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [12] reserved 0: direct 1: indirect ssr index (applicable if dq[29] is indirect) id bank 0 or 1 10: external sram reserved if dq[29] is 0, this field carries the address of the sram location. if dq[29] is 1, the ssr index specified on dq[28:26] is used to generate the address of the sram location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [12] notes: 11. the latency of the sram read will be different than the one described above (see subsection 12.1, ?sram pio access,? on page 8 6). table 10-4 lists and describes the format of the read address for a data array, mask array, or sram. 12. ?|? stands for logical or operation. ?{}? stands for concatenation operator. cycle cycle cycle cycle cycle cycle address xdata 123456 clk2x cmdv cmd[1:0] ack dq cmd[10:2] phs_l figure 10-1. single-lo cation read cycle timing a b read
cynse70256 document #: 38-02035 rev. *e page 22 of 109 the read operation lasts 4 + 2n clk cycles (where n is the number of accesses in the burst specified by the blen field of the rburreg) in the sequence shown below. this operation assu mes that the host asic has prog rammed the rburreg of the approprritae bank of the device with the starting adr and the bl en before initiating the burst read command for the appropriate bank in the appropriate device. ? cycle 1 : the host asic applies the read instruction on cmd[1:0] (cmd[2] = 1) using cmdv = 1, and the address supplied on the dq bus as shown in table 10-6 . the host asic selects the bank 0 or 1 (b ased on bank bit) of the cynse70256 device where id[4:1] matches the dq[25: 22] lines. dq[21] specfies the bank of the devic e that is written. if dq[25:21] = 11111 the host asic selects the bank of the cynse70256 device with the ldev bit set. ? cycle 2 : the host asic floats dq[71:0] to a three-state condition. ? cycle 3 : the host asic keeps dq[71:0] in a three-state condition. ? cycle 4 : the selected device starts to drive the dq[71: 0] bus and drives ack and eot from z to low. ? cycle 5: the selected device drives the read data from the addres s location on the dq[71:0] bus and drives the ack signal high. cycles 4 and 5 repeat for each additional access until all the accesses specified in the blen field of rburreg are complete. on the last transfer, the cynse70256 device drives the eot signal high. ? cycle (4 + 2n) : the selected device drives the dq[71:0] to a three- state condition, and drives the ack and eot signals low. at the termination of cycle (4 + 2n), the selected device floats the ack line to a three-state condition. the burst read instru ction is complete, and a new operation can begin. table 10-6 describes the read address format for data and mask arrays for burst read operations. 10.4 write command the write command can be a single write of a data array, mask arra y, register, or external sram location (cmd[2] = 0). it can be a burst write (cmd[2] = 1) using an internal auto-increm enting address registers (wbura dr) of the data or mask array table 10-5. read address fo rmat for intern al registers dq[71:26] dq[25:22] dq[21] dq[20:19] dq[18:7] dq[6:0] reserved id bank 0 or 1 11: register reserved register address table 10-6. read address format for data and mask arrays dq[71:26] dq[25:22] dq[21] dq [20:19] dq[18:16] dq[15:0] reserved id bank 0 or 1 00: data array reserved do not care . these seventeen bits come from the rburadr, which increments for each access. reserved id bank 0 or 1 01: mask array reserved do not care . these seventeen bits come from the rburadr, which increments for each access. cmdv cmd[1:0] ack eot dq ff ff data1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle 12 data0 data2 ff data3 ff phs_l cmd[10:2] address a b read clk2x figure 10-2. burst read of the data and mask arrays (blen = 4)
cynse70256 document #: 38-02035 rev. *e page 23 of 109 locations. a single-location write is a three-cycle operation, as shown in figure 10-3 . the burst write adds one extra cycle for each successive location write. the following is the write operation sequence. ta ble 10 -7 shows the write address format for the data array, the mask array, or single-write sram. table 10-8 shows the write address format for the internal registers. ? cycle 1a: the host asic applies the write instru ction to cmd[1:0] (cmd[2] = 0) usin g cmdv = 1, and the address supplied on the dq bus. the host asic also supplies the gmr index to mask the write to the data or mask array location on {cmd[10], cmd[5:3]}. for sram writes, th e host asic must supply the sadr[23:21] on cmd[ 8:6]. the host asic sets cmd[9] to 0 for a normal write. ? cycle 1b: the host asic continues to apply the write instruction to cmd[1:0] (cmd[2] = 0) using cmdv = 1, and the address supplied on the dq bus. the host asic continues to supply the gmr index to mask the write to the data or mask array locations in {cmd[10], cmd[5:3]}. the host asic selects the device where id[4:1] matches th e dq[25:22] lines and the bank within the device using value on dq[21], or it select s both banks of all the devices when dq[25:21] = 11111. ? cycle 2: the host asic drives dq[71:0] with the dat a to be written to the data array, mask array, or register location of the selected device. ? cycle 3: idle cycle. at the termination of cycle 3, another operation can begin. [13] table 10-7. write address format for data a rray, mask array, or sram (single write) dq [71:30] dq [29] dq [28:26] dq [25:22] dq [21] dq [20:19] dq [18:16] dq [15:0] reserved 0: direct 1: indirect ssr (applicable if dq[29] is indirect) id bank 0 or 1 00: data array reserved if dq[29] is 0, this field carries the address of the data array location. if dq[29] is 1, the ssr specified on dq[28:26] is used to generate the address of data array location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [14] reserved 0: direct 1: indirect ssr (applicable if dq[29] is indirect) id bank 0 or 1 01: mask array reserved if dq[29] is 0, this field carries the address of the mask array location. if dq[29] is 1, the ssr specified on dq[28:26] is used to generate the address of the mask array location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [14] reserved 0: direct 1: indirect ssr (applicable if dq[29] is indirect) id bank 0 or 1 10: external sram reserved if dq[29] is 0, this field carries the address of the sram location. if dq[29] is 1, the ssr specified on dq[28:26] is used to generate the address of sram location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]}. [14] table 10-8. write address format for internal registers dq[71:26] dq[25:22] dq[21] dq[20:19] dq[18:7] dq[6:0] reserved id bank 0 or 1 11: r egister reserved register address notes: 13. the latency of the sram write will be different than the one described above (see subsection 12.1, ?sram pio access,? on page 86). 14. ? | ? stands for logical or operation. ?{}? stands for concatenation operator. cycle 2 cycle 3 write address data cmdv cmd[1:0] dq x cycle 1 cycle 0 cycle 4 cmd[10:2] b phs_l a clk2x figure 10-3. single write cycle timing
cynse70256 document #: 38-02035 rev. *e page 24 of 109 figure 10-4 shows the timing diagram of a burst write operation of the data or mask array. the burst write operation lasts for (n + 2) clk cycles. n signifies the number of accesse s in the burst as s pecified in the ble n field of the wburreg register. the following is the block writ e operation sequence. this operat ion assumes that the host asic has programmed the wburreg of the approp riate bank with the starting adr and blen before initiating a burst write command. ? cycle 1a: the host asic applies the write instru ction to cmd[1:0] (cmd[2] = 1) usin g cmdv = 1, and the address supplied on the dq bus as shown in table 10-9 . the host asic also supplies the gmr index to mask the write to the data or mask array locations in {cmd[10], cmd[5:3]}. the hos t asic sets cmd[9] to 0 for the normal write. ? cycle 1b: the host asic continues to apply the wr ite instruction on cmd[1:0] (cmd[2] = 1) using cmdv = 1, and the address supplied on the dq bus. the host asic continues to supply the gmr index to mask the write to the data or mask array locations in {cmd[10], cmd[5:3]}. the hos t asic selects the device for which id[4:1] matches the dq[25:22] lines and the bank of the device using dq[21] lines. it selects all devices when dq[25:21] = 11111. ? cycle 2: the host asic drives the dq[71:0] with the data to be wr itten to the data or mask array location of the selected device. the cynse70256 device writes the data from the dq[71:0] bus only to the subfield with the corresponding mask bit set to 1 in the gmr that is specified by th e index {cmd[10],cmd[5:3 ]} supplied in cycle 1. ? cycles 3 to n + 1: the host asic drives the dq[71:0] with the data to be written to the next data or mask array location of the selected device (addressed by the auto-i ncrement adr field of the wburreg register). the cynse70256 device writes the data on the dq[71:0] bus only to t he subfield that has the corresponding mask bit set to 1 in the gmr specified by the index supplied in cycle 1 {cmd[10] ,cmd[5:3]}. the cynse70256 device drives the eot signal low from cycle 3 to cycle n; the cynse70256 device drives the eot signal high in cycle n + 1 (n is specified in the blen field of the wburreg). ? cycle n + 2: the cynse70256 device drives the eot signal low. at the termination of cycle n + 2, the cynse70256 device floats the eot signal to a three-state operation, and a new instructio n can begin. 10.5 parallel write in order to write the data and mask arraysof both banks faster fo r initialization, testing, or di agnostics, many locations can be written simultaneously in the cynse70256 device. when cmd[ 9] is set in cycles a and b of the write command during a write to the data or mask arrays, the address present on dq[10:1] that specifies 128 locations in the device is used, and 64 72-bit locations are simultaneously written in either the data or mask a rray. setting dq[21] to 0 will cause a write to the addresses, specified by dq[10:1], closer to address 0, while setting dq[ 21] to 1 will cause a write to the addresses, also specified by dq[10:1], further from address 0. table 10-9. write address format for data and mask array (burst write) dq [71:26] dq [25:22] dq [21] dq [20:19] dq [18:16] dq [15:0] reserved id bank 0 or 1 00: data array reserved do not care . these seventeen bits come from wburadr, which increments with each access. reserved id bank 0 or 1 01: mask array reserved do not care . these seventeen bits come from wburadr, which increments with each access. 1 data0 data1 data2 data3 write address cyc l e 2 cyc l e 3 cyc l e 4 cyc l e 5 cyc l e 6 cyc l e cmd[1:0] dq clk2x eot cmd[10:2] a b phs_l cmdv x figure 10-4. burst write of the data and mask arrays (blen = 4)
cynse70256 document #: 38-02035 rev. *e page 25 of 109 10.6 search command this subsection describes the following. ? 72-bit search on tables configured as 72 using up to four devices ? 72-bit search on tables configured as 72 using up to fifteen devices ? 144-bit search on tables configured as 144 using up to four devices ? 144-bit search on tables configured as 144 using up to fifteen device ? 288-bit search on tables configured as 288 using up to four devices ? 288-bit search on tables configured as 288 using up to fifteen devices ? mixed-size search on tables configured with di fferent widths using an cynse70256 with cfg_l low ? mixed-size searches on tables configured with differ ent widths using an cynse70256 with cfg_l high. 10.6.1 72-bit search on tables configured as 72 using up to four cynse70256 devices the hardware diagram of th e search subsystem of four devices is shown in figure 10-5 . the following are the parameters programmed into each bank of the the four devices. ? first three devices (dev ices 0?2, both banks): cfg = 0000000000000000, tlsz = 01, hlat = 010, lram = 0, and ldev = 0 . ? fourth device (device 3, bank 0): cfg = 0000000000000000, tlsz = 01, hlat = 010, lram = 0, and ldev = 0 ? fourth device (device 3, bank 1): cfg = 0000000000000000, tlsz = 01, hlat = 010, lram = 1, and ldev = 1 . [15] figure 10-6 shows the timing diagram for a search command in the 72 -bit-configured table of four devices for device number 0. figure 10-7 shows the timing diagram for a search command in the 72 -bit-configured table of four devices for device number 1. figure 10-8 shows the timing diagram for a search command in the 72-bit-configured table of four devices for device number 7 (the last device in this specific tabl e). for these timing diagrams four 72-bit searches are performed sequentially. hit/miss assumptions were made as shown below in table 10-10 . note: 15. each bank of the four devices must be programmed with the same values for tlsz and hlat. only the the last bank of the last device in the table (device number 3 in this case) must be programmed with lram = 1 and ldev = 1. table 10-10. hit/miss assumptions search number 1 2 3 4 device 0 hit miss hit miss device 1 miss hit hit miss device 2 miss miss miss miss device 3 miss miss hit hit lho[0] 0123456 lhi lho[0] 01 34 56 lhi lho[1] 0123 456 lhi lho[0] 012345 6 lhi lho[0] lho[1] lho[1] lho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram cynse70256 #0 cynse70256 #1 cynse70256 #2 cynse70256 #3 2 bho[2] cmdv cmd[10:0] ssf, ssv figure 10-5. hardware diagram for a table with four devices
cynse70256 document #: 38-02035 rev. *e page 26 of 109 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (this cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 0000000000000000, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the bool ean ?or? of the entire bus lhi[6:0]. note: |lho[1:0] is logical ?o r? of lho[0] and lho[1]. phs_l sadr[23:0] ssf ssv ale_l search1 search3 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b a1 a3 z z z z z z z z z z z z z z z 0 0 1 0 0 1 1 1 1 1 z z z z device is the global winner.) (this device is the global winner.) |(lhi[6:0]) 0 this device.) (miss on this device.) | lho[1:0] search2 (miss on figure 10-6. timing diagram for 72-bit search device number 0
cynse70256 document #: 38-02035 rev. *e page 27 of 109 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (miss cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search3 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b a2 z z z z 1 1 z z (local winner but not global winner.) (miss on this device.) |(lhi[6:0]) |lho[1:0] z 0 z z 0 z z 1 z on this device.) (this device winner.) is global c fg = 0000000000000000, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the bool ean ?or? of the ent ire bus lhi[6:0]. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-7. timing diagram for 72-bit search device number 1
cynse70256 document #: 38-02035 rev. *e page 28 of 109 the following is the sequence of operation for a single 72-bit search command (also refer to subsection 10.2, ?commands and command parameters,? on page 19). ? cycle a : the host asic drives cmdv high and a pplies search command code (10) to cm d[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[ 8:6] signals must be driven with the same bits that will be driven on sadr[2 3:21] by this device if it has a hit. dq[71:0] must be driven with the 72-bit data t o be compared. the cmd[2] signal must be driven to logic 0. ? cycle b : the host asic continues to drive cmdv high and to app ly search command code (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for st oring the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and hit flag (see page 14 for a description of ssr[0:7]). the dq[71:0] continues to carry the 72-bit data to be compared. note . for 72-bit searches, the host asic must supply the same 72-bit da ta on dq[71:0] during both cycles a and b. also, the even and odd pairs of gmrs selected for the co mparison must be programmed with the same value. the logical 72-bit search operation is shown in figure 10-9 . the entire table of 72-bit entries (four devices) is compared to a 72-bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and local mask bits. the effective gmr is the 72-bit word specified by the i dentical value in both even and odd gmr pairs, in each of two banks of the four device s, and selected by the gmr index in the command?s cycle a. the 72 -bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd compara nd register pairs (selected by the comparand register index in cycle clk2x cmdv cmd[1:0] dq ce_l oe_l (miss on cmd[10:2] search2 search4 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv search1 search2 search3 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b a4 0 (local winner but not global winner.) |(lhi[6:0]) |lho[1:0] this device.) (miss on this device.) 0 z 0 0z 0 ale_l we_l 1z 1 0 z 1 0 0 z 1 0 search4 (global winner.) z cfg = 0000000000000000, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the bool ean ?or? of the entire bus lhi[6:0]. note: |lho[1:0] is logical ?o r? of lho[0] and lho[1]. figure 10-8. timing diagram for 72-bit search device number 3 (last device)
cynse70256 document #: 38-02035 rev. *e page 29 of 109 command cycle b) in each of the four devices. in the 72 conf iguration, only the even comparand register can subsequently be used by the learn command in one of the devices (the first n on-full device only). the word k (presented on the dq bus in both cycles a and b of the command) is compared with each entry in the table, starting at location 0. the first matching entry?s loc ation address l is the winning address that is driv en as part of the sram address on the sadr[23:0] lines (see section 12.0, ?sram addressing,? on page 86). the global winning device will drive the bus in a specific cycle. on a global miss cycle, the device wi th lram = 1 (default driving device for the sram bus) and ldev = 1 (default driving de vice for ssf and ssv si gnals) will be the default driver for such missed cycles. the search command is a pipelined operation and executes a s earch at half the rate of t he frequency of clk2x for 72-bit searches in 72-configured tables. the latency of sadr, ce_l , ale_l, we_l, ssv, and ssf from the 72-bit search command cycle (two clk2x cycles) is shown in ta ble 10 -11 . the latency of the se arch from command to sram access cycle is 5 for up to four devices in the table (tlsz = 01). ssv and ssf also shift further to the right for di fferent values of hlat, as specified in table 10-12 . 10.6.2 72-bit search on tables configured as 72 using up to fifteen cynse70256 devices the hardware diagram of the search subsystem of fifteen devices is shown in figure 10-10 . each of the four blocks in the diagram represents four cynse70256 devices (except the last, which has three devices). the diagram for a block of four devices is shown in figure 10-11 . the following are the parameters programmed into the fifteen devices. table 10-11. search latency from instruction to sram access cycle number of devices max tabl e size latency in clk cycles 1?4 (tlsz = 01) 512k 72 bits 5 1?15 (tlsz = 10) 1920k 72 bits 6 table 10-12. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 0000000000000000 71 0 location 0 1 2 3 524,287 (72-bit configuration) address k gmr comparand register (odd) comparand register (even) k k 71 0 71 0 (first matching entry) l must be same in each of the banks each of the four devices will be same in each two banks of the four devices figure 10-9. 72 table with four devices
cynse70256 document #: 38-02035 rev. *e page 30 of 109 ? first thirty devices (devices 0?13, both banks): cfg = 0000000000000000, tlsz = 10, hlat = 001, lram = 0, and ldev = 0. ? first thirty devices (device 14, b ank 0): cfg = 0000000000000000, tlsz = 10, hlat = 001, lram = 0, and ldev = 0. ? thirty-first device (device 14, bank 1): cfg = 00000000 00000000, tlsz = 10, hlat = 001, lram = 1, and ldev = 1. note . all fifteen devices must be programmed with the same values for tlsz and hlat. only the last bank of the last device in the table must be programmed with lram = 1 and ldev = 1 (device number 14 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 10-13 . for the purpose of illustrating the timings, it is further a ssumed that the there is only one device with a matching entry in each of the blocks. figure 10- 12 shows the timing diagram for a search command in the 72-bit-conf igured table of fifteen devices for each of the four devices in block number 0. figure 10-13 shows the timing diagram for a search command in the 72-bit-configured table of fifteen devices for the all the devices in block number 1 (above the winning device in that block). figure 10-14 shows the timing diagram for the globally winning device (defined as the final winner within its own a nd all blocks) in block number 1. figure 10-15 shows the timing diagram for all the devices below the globally winning device in block number 1. figure 10-16 , figure 10-17 , and figure 10-18 show the timing diagrams of the devices above the globally win ning device, the globally winning device, and the devices below the globally winning device, respectively, for block number 2. figure 10-19 , figure 10-20 , figure 10-21 , and figure 10-22 show the timing diagrams of the devices above globally winning device, the globally winning device, and the devices below the global ly winning device except the last device (device 14), respectively, for block number 3. the 72-bit search operation is pipelined and executes as follows. four cycles from th e search command, each of the devices knows the outcome internal to it for that operation. in the fifth cycle after the search co mmand, the devices in a block arbitr ate for a winner among them (a ?block? being defined as less than or equal to four devices resolving the winner within them using the lhi[6:0] and lho[1:0] signalling mechanism). in the sixth cycle after the search command, the blocks (of devices) resolve the winning block through the bhi[2:0] and bho[2:0] signalling mechanism. the winning device within the winning block is the global winning device for a search operation. table 10-13. hit/miss assumptions search number 1 2 3 4 block 0missmissmissmiss block 1 miss miss hit miss block 2 miss hit hit miss block 3 hit hit miss miss gnd bho[2] block of 8 cynse70256s block 0 bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70256s block 3 bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70256s block 1 block of 8 cynse70256s block 2 dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv (devices 4?7) (devices 8?11) (devices 12?14) (devices0?3) figure 10-10. hardware diagram for a table with fifteen devices
cynse70256 document #: 38-02035 rev. *e page 31 of 109 lho[0] 0123456 lhi lho[0] 01 34 56 lhi lho[1] 0123 456 lhi lho[0] 012345 6 lhi lho[0] lho[1] lho[1] lho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram cynse70256 #0 cynse70256 #1 cynse70256 #2 cynse70256 #3 2 bho[2] cmdv cmd[10:0] ssf, ssv figure 10-11. hardware diagram for a block of up to four devices cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the bool ean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 (miss on this device.) (miss on this device.) figure 10-12. timing diagra m for each device in block number 0 (miss on each device)
cynse70256 document #: 38-02035 rev. *e page 32 of 109 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 (miss on this device.) (miss on this device.) (miss on this device.) (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boole an ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-13. timing diagram for each device above the winning device in block number 1
cynse70256 document #: 38-02035 rev. *e page 33 of 109 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 global winner.) |(lhi[6:0]) 0 bho[2:0] 0 a3 (miss on this device.) (miss on this device.) (miss on this device.) (this device cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-14. timing diagram for globally winning device in block number 1
cynse70256 document #: 38-02035 rev. *e page 34 of 109 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z |lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the bool ean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-15. timing diagram for devices below the winning device in block number 1
cynse70256 document #: 38-02035 rev. *e page 35 of 109 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 (miss on this device.) (miss on this device.) (miss on this device.) (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands fo r the boolean ?or? of t he entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-16. timing diagram for devices ab ove the winning device in block number 2
cynse70256 document #: 38-02035 rev. *e page 36 of 109 cyc l e clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cyc l e 2 cyc l e 3 cyc l e 4 cyc l e 5 cyc l e 6 cyc l e 7 cyc l e 8 cyc l e 9 cyc l e 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z |lho[1:0] 0 (global winner.) i(bhi[2:0]) 0 search3 (hit but not winner.) |(lhi[6:0]) 0 bho[2:0] 0 a2 0 z 0 1 1 1 z z z z z z (miss on this device.) (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boole an ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-17. timing diagram for globally winning device in block number 2
cynse70256 document #: 38-02035 rev. *e page 37 of 109 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 z search3 (miss on this device.) search2 (miss on this device.) search4 (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of t he entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-18. timing diagram for devices below the winning device in block number 2
cynse70256 document #: 38-02035 rev. *e page 38 of 109 cyc l e clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cyc l e 2 cyc l e 3 cyc l e 4 cyc l e 5 cyc l e 6 cyc l e 7 cyc l e 8 cyc l e 9 cyc l e 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 (miss on this device.) search3 |(lhi[6:0]) 0 bho[2:0] 0 z (miss on this device.) (miss on this device.) (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of t he entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-19. timing diagram for devices ab ove the winning device in block number 3
cynse70256 document #: 38-02035 rev. *e page 39 of 109 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z |lho[1:0] 0 (hit but not global winner.) i(bhi[2:0]) 0 (global winner.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a1 0 z 0 1 1 1 z z z z z z (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-20. timing diagram for globally winning device in block number 3
cynse70256 document #: 38-02035 rev. *e page 40 of 109 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z |lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) search3 |(lhi[6:0]) 0 bho[2:0] 0 z (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands fo r the boolean ?or? of t he entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-21. timing diagram for devices below the winning device in block number 3 (except the last device [device 14])
cynse70256 document #: 38-02035 rev. *e page 41 of 109 the following is the sequence of operation for a single 72-bit search command (also refer to subsection 10.2, ?commands and command parameters,? on page 19). ? cycle a : the host asic drives cmdv high and applies search comm and code (10) on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[ 8:6] signals must be driven with the same bits that will be driven on sadr[2 3:21] by this device if it has a hit. dq[71:0] must be driven with the 72-bit data t o be compared. the cmd[2] signal must be driven to a logic 0. ? cycle b : the host asic continues to drive cmdv high and applies search command (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand re gister pair for storing the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be dr iven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see page 14 for the descrip tion of ssr[0:7]). the dq[71:0] continues to carry the 72-bit data to be compared. note . for 72-bit searches, the host asic must supply the same 72-bit data on dq[71:0] during both cycles a and b. the even and odd pair of gmrs selected for the comp are must be programmed with the same value. the logical 72-bit search operation is shown in figure 10-23 . the entire table (fifteen devices of 72-bit entries) is compared to a 72-bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and local mask bits. the effective gmr is the 72-bit word specified by the identical val ue, in both even and odd gmr pairs in each of banks in each of t he fifteen devices, a nd selected by the gmr index in the command?s cycle a. the 72-bit word k (presented on t he dq bus in both cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z 0 0 |lho[1:0] 0 (global miss; this device default driver.) i(bhi[2:0]) 0 (hit on some device above.) search3 |(lhi[6:0]) 0 bho[2:0] 0 z 0 0 0 z 1 z 1 0 0 z z 0 1 (hit on some device above.) (hit on some device above.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the bool ean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the bool ean ?or? for the ent ire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-22. timing diagram for d evice number 3 in block number 3 (device 14 in depth-cascaded table)
cynse70256 document #: 38-02035 rev. *e page 42 of 109 cycles a and b of the command) is also stor ed in both even and odd comparand register pa irs, in each of the banks of all fiftee n devices, and selected by the comparand register index in comma nd cycle b. in the 72 configurati on, the even comparand register can be subsequently used by the learn comm and only in the first non-full device. the word k (presented on the dq bus in both cycles a and b of the command) is compared with each entry in the table, starting at location 0. the first matching entry?s loc ation address l is the winning address that is driven as part of the sram address on the sadr[23:0 ] lines (see ?sram addressing? on page 86). the global winning device will drive the bus in a specific cycle. on global miss cycles, th e device with lram = 1 and ldev = 1 will be t he default driver for such missed cycles. the search command is a pipelined operation and executes a s earch at half the rate of t he frequency of clk2x for 72-bit searches in 72-configured tables. the latency of sadr, ce_l , ale_l, we_l, ssv, and ssf from the 72-bit search command cycle (two clk2x cycles) is shown in table 10-14 . for up to fifteen devices in the table (with tlsz = 10) , the latency of the search from co mmand to sram access cycle is 6. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 10-15 . 10.6.3 144-bit search on tables configured as 144 using up to four cynse70256 devices the hardware diagram of the search subs ystem of four devices is shown in figure 10-24 . the following are parameters that are programmed into the four devices. ? first three devices (devices 0?2, banks 0 and 1): cfg = 0101010101010101, tlsz = 01, hlat = 010, lram = 0, and ldev = 0. ? first three devices (devices 3, bank 0): cfg = 0101010 101010101, tlsz = 01, hlat = 010, lram = 0, and ldev = 0. ? fourth device (device 3, bank 1): cfg = 0101010101010101, tlsz = 01, hlat = 010, lram = 1, and ldev = 1. table 10-14. search latency from instruction to sram access cycle number of devices max table size latency in clk cycles 1?4 (tlsz = 01) 512k 72 bits 5 1?15 (tlsz = 10) 1920 k 72 bits 6 table 10-15. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 0000000000000000 71 0 location 0 1 2 3 1966079 (72-bit configuration) address k gmr comparand register (odd) comparand register (even) k k 71 0 71 0 (first matching entry) l must be same in each of the banks of each of the fifteen devices will be same in each of the banks of each of the fifteen devices figure 10-23. 72 table with fifteen devices
cynse70256 document #: 38-02035 rev. *e page 43 of 109 note . all four devices must be programmed wit h the same value of tlsz and hlat. only the last bank of the last device in the table must be programmed with lram = 1 and ldev = 1 (device number 3 in this case). figure 10-25 shows the timing diagram for a search command in the 144- bit-configured table of four devices for device number 0. figure 10-26 shows the timing diagram for a search command in the 144-b it-configured table consisting of four devices for device number 1. figure 10-27 shows the timing diagram for a search command in the 144-bit configured table consisting of four devices for device number 3 (the last device in this specific table) . for these timing diagrams, the four 144-bit searches are performe d sequentially, and the following hit/miss assumptions are made (see table 10-16 ). table 10-16. hit/miss assumptions search number 1 2 3 4 device 0 hit miss hit miss device 1 miss hit hit miss devices 2?6 miss miss miss miss device 7 miss miss hit hit lho[0] 0123456 lhi lho[0] 01 34 56 lhi lho[1] 0123 456 lhi lho[0] 012345 6 lhi lho[0] lho[1] lho[1] lho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram cynse70256 #0 cynse70256 #1 cynse70256 #2 cynse70256 #3 2 bho[2] cmdv cmd[10:0] ssf, ssv figure 10-24. hardware diagra m for a table with four devices
cynse70256 document #: 38-02035 rev. *e page 44 of 109 cfg = 0101010101010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the bool ean ?or? of the entire bus lhi[6:0]. note: |lho[1:0] is logical ?o r? of lho[0] and lho[1]. cycle clk2x cmdv cmd[1:0] ce_l oe_l (this device cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search3 search4 01 01 01 01 search1 search3 a b a b a b a b a1 a3 z z z z z z z z z z z z z z z 0 0 1 0 0 1 1 1 1 1 z z z z is the global winner.) |(lhi[6:0]) 0 (miss on this device.) |lho[1:0] a b a b a b a b dq d1 d2 d3 d4 (this device is the global winner.) (miss on this device.) figure 10-25. timing diagram for 144-bit search device number 0
cynse70256 document #: 38-02035 rev. *e page 45 of 109 cycle clk2x cmdv cmd[1:0] ce_l oe_l (miss on cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search3 search4 01 01 01 01 search1 search3 a b a b a b a b a2 z z z z 1 1 z z (local but not global winner.) lhi[6:0] |lho[1:0] z 0 z z 0 z z 1 z (this device global winner.) a b a b a b a b dq d1 d2 d3 d4 this device.) (miss on this device.) cfg = 0101010101010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the boolean ?or? of the entire bus lhi[6:0]. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-26. timing diagram for 144-bit search device number 1
cynse70256 document #: 38-02035 rev. *e page 46 of 109 the following is the sequence of operation for a single 144- bit search command (also see subsection 10.2, ?commands and command parameters,? on page 19). ? cycle a : the host asic drives cmdv high and applies search comm and code (10) on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[ 8:6] signals must be driven with the same bits that will be driven by this device on sadr[23:21] if it has a hit. dq [71:0] must be driven with the 72-bit data ([143:72]) in order to be compared against all even loca tions. the cmd[2] signal must be driven to logic 0. ? cycle b : the host asic continues to drive cmdv high and to app ly search command code (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the compar and register pair for storin g the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the ssr index that will be used for storing the address of the matching entry and the hit flag (see page 14 for the description of ssr[0:7]). t he dq[71:0] is driven with 72-bit data ([71:0]) compared again st all odd locations. cycle clk2x cmdv cmd[1:0] ce_l oe_l (miss on cmd[10:2] search2 search4 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv search1 search2 search3 search4 01 01 01 01 search1 search3 a b a b a b a b a4 0 (local but not global winner.) (global winner.) |(lhi[6:0]) |lho[1:0] this device.) (miss on this device.) 0 z 0 0 z 0 ale_l we_l 1z 1 0 z 1 0 0 z 1 0 a b a b a b a b dq d1 d2 d3 d4 cfg = 0101010101010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the boolean ?or? of the entire bus lhi[6:0]. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-27. timing diag ram for 144-bit search device number 7 (last device)
cynse70256 document #: 38-02035 rev. *e page 47 of 109 the logical 144-bit search operation is shown in figure 10-28 . the entire table (four devices of 144-bit entries) is compared to a 144-bit word k (presented on the dq bus in cycles a and b of the co mmand) using the gmr and local mask bits. the gmr is the 144-bit word specified by the even and odd global mask pair selected by the gmr index in the command?s cycle a. the 144- bit word k (presented on the dq bus in cycles a and b of the co mmand) is also stored in the ev en and odd comp arand registers specified by the comparand register inde x in command cycle b. in 144 configuratio ns, the even and odd comparand registers can be subsequently used by the learn command in only one of the devices (the first non-full device). the word k (presented on the dq bus in cycles a and b of the command) is compared to each entry in the table st arting at location 0. the first matching entry?s location, address l, is the winning address that is driv en as part of the sram addre ss on the sadr[23:0] lines (see ?sr am addressing? on page 86). the global winning device will drive the bus in a specific cycle. on global miss cycles the device with lram = 1 (the default driving device for the sram bus) and ldev = 1 (the default driving device for ssf and ssv signals) will be the default driver for such missed cycles. [16] the search command is a pipelined operation and executes a search at half the rate of the frequency of clk2x for 144-bit searches in 144-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 144-bit search command cycle (two clk2x cycles) is shown in table 10-17 . for one to four devices in the table and tlsz = 01, search la tency from command to sram access cycle is 5. in addition, ssv and ssf shift further to the right for diff erent values of hlat, as specified in table 10-18 . note: 16. during 144-bit searches of 144-bit-configured tables, the search hit will always be at an even address. table 10-17. search latency from instruction to sram access cycle number of devices max table size latency in clk cycles 1?4 (tlsz = 01) 256k 144 bits 5 1?15 (tlsz = 10) 960k 144 bits 6 table 10-18. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 0101010101010101 143 0 location 0 2 4 6 524,286 (144-bit configuration) address k gmr comparand register (odd) comparand register (even) a b 143 0 71 0 (first matching entry) l a b even odd will be same in each of the banks of the four devices must be same in each of the banks for each of the four devices figure 10-28. 144 table with four devices
cynse70256 document #: 38-02035 rev. *e page 48 of 109 10.6.4 144-bit search on tables configured as 144 using up to fifteen cynse70256 devices the hardware diagram of the search subsystem of fifteen devices is shown in figure 10-29 . each of the four blocks in the diagram represents a block of four cynse70256 dev ices (except the last, which has three dev ices). the diagram for a block of four devices is shown in figure 10-30 . the following are the parameters programmed into the fifteen devices. ? first fourteen devices (devices 0?13, bank 0 and 1): cf g = 0101010101010101, tlsz = 10, hlat = 001, lram = 0, and ldev = 0. ? fifteenth device (device 14, bank 0): cfg = 0101010101010101, tlsz = 10, hlat = 001, lram = 0, and ldev = 0 . ? fifteenth device (device 14, bank 1): cfg = 0101010101010101, tlsz = 10, hlat = 001, lram = 1, and ldev = 1 . [17] the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 10-19 . for the purpose of illustrating the timings, it is further a ssumed that the there is only one device with a matching entry in each of the blocks. figure 10- 31 shows the timing diagram for a search command in the 144-bit-co nfigured table (fifteen devices) for each of the four devices in block number 0. figure 10-32 shows the timing diagram for a search command in the 144-bit-configured table (fifteen devices) for all the devices above the winning device in block number 1. figure 10-33 shows the timing diagram for the globally winning device (the final winner within its own and all blocks) in block number 1. figure 10-34 shows the timing diagram for all the devices below the globally winning device in block number 1. figure 10-35 , figure 10-36 , and figure 10-37 show the timing diagrams of the devices above globally winning device, the globally winning device, and the devices below the globally winning device, respectively, for block number 2. figure 10-38 , figure 10-39 , figure 10-40 , and figure 10-41 show, respectively, the timing diagrams of the devices above the globally winning device, the globally winning device, and devices below the globally winning device except the last device (device 14), and then the last device (device 14) for block number 3. the 144-bit search operation is pipelined and executes as follows. in the fifth cycle after the search command, the devices in a block (being less than or equal to four devices resolving the winner within them using the lh i[6:0] and lho[1: 0] signalling mechanism) arbitrate for a winne r among them. in the sixth cycle after the search comm and, the blocks (of de vices) resolve the winning block through the bhi[2:0] and bho[2:0] signalling mechanism. the winning device in the winning block is the global winning device for a search operation. table 10-19. hit/miss assumptions search number1234 block 0 miss miss miss miss block 1 miss miss hit miss block 2 miss hit hit miss block 3 hit hit miss miss note: 17. all fifteen devices must be programmed with the same value of tlsz and hlat. only the last bank of the last device in the ta ble must be programmed with lram = 1 and ldev = 1 (device number 30 in this case).
cynse70256 document #: 38-02035 rev. *e page 49 of 109 bho[2] block of 8 cynse70256s block 0 bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70256s block 3 bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70256s block 1 block of 8 cynse70256s block 2 dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv (devices 0?3) (devices 4?7) (devices 8?11) (devices 12?14) figure 10-29. hardware diagram for a table with fifteen devices lho[0] 0123456 lhi lho[0] 01 34 56 lhi lho[1] 0123 456 lhi lho[0] 012345 6 lhi lho[0] lho[1] lho[1] lho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram cynse70256 #0 cynse70256 #1 cynse70256 #2 cynse70256 #3 2 bho[2] cmdv cmd[10:0] ssf, ssv figure 10-30. hardware diagra m for a table with four devices
cynse70256 document #: 38-02035 rev. *e page 50 of 109 cycle clk2x cmdv cmd[1:0] dq ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg =01001010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the bool ean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 d1 d2 d3 d4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 (miss on this device.) (miss on this device.) (miss on this device.) (miss on this device.) figure 10-31. timing diagra m for each device in block number 0 (miss on each device)
cynse70256 document #: 38-02035 rev. *e page 51 of 109 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 (miss on this device.) search3 |(lhi[6:0]) 0 bho[2:0] 0 a b a b a b a b dq d1 d2 d3 d4 (miss on this device.) (miss on this device.) (miss on this device.) cfg =01001010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the b oolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?o r? of lho[0] and lho[1]. figure 10-32. timing diagram for each device above the winning device in block number 1
cynse70256 document #: 38-02035 rev. *e page 52 of 109 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z |lho[1:0] 0 (miss on this device.) (miss on this device.) i(bhi[2:0]) 0 (miss on this device.) (this device global winner.) |(lhi[6:0]) 0 bho[2:0] 0 a3 a b a b a b a b dq d1 d2 d3 d4 1zz 1z 1z 0 z 0 z z search3 cfg =01001010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the b oolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?o r? of lho[0] and lho[1]. figure 10-33. timing diagram for globally winning device in block number 1
cynse70256 document #: 38-02035 rev. *e page 53 of 109 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 a b a b a b a b dq d1 d2 d3 d4 (miss on this device.) (miss on this device.) (miss on this device.) (miss on this device.) lho[1:0] cfg =01001010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-34. timing diagram for devices below the winning device in block number 1
cynse70256 document #: 38-02035 rev. *e page 54 of 109 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 a b a b a b a b dq d1 d2 d3 d4 (miss on this device.) (miss on this device.) (miss on this device.) (miss on this device.) cfg =01001010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boo lean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-35. timing diagram for devices ab ove the winning device in block number 2
cynse70256 document #: 38-02035 rev. *e page 55 of 109 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z |lho[1:0] 0 (global winner.) i(bhi[2:0]) 0 search3 (hit but not winner.) |(lhi[6:0]) 0 bho[2:0] 0 a2 0 z 0 1 1 1 z z z z z z a b a b a b a b dq d1 d2 d3 d4 (miss on this device.) (miss on this device.) cfg =01001010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the bool ean ?or? for the ent ire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-36. timing diagram for globally winning device in block number 2
cynse70256 document #: 38-02035 rev. *e page 56 of 109 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z a b a b a b a b dq d1 d2 d3 d4 (miss on this device.) (miss on this device.) (miss on this device.) (miss on this device.) cfg =01001010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the b oolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?o r? of lho[0] and lho[1]. figure 10-37. timing diagram for devices below the winning device in block number 2
cynse70256 document #: 38-02035 rev. *e page 57 of 109 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z a b a b a b a b dq d1 d2 d3 d4 (miss on this device.) (miss on this device.) (miss on this device.) (miss on this device.) cfg =01001010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boole an ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-38. timing diagra m for devices above the winning device in block number 3
cynse70256 document #: 38-02035 rev. *e page 58 of 109 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z |lho[1:0] 0 (hit but not global winner.) (miss on this device.) i(bhi[2:0]) 0 (global winner.) search3 (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a1 0 z 0 1 1 1 z z z z z z a b a b a b a b dq d1 d2 d3 d4 cfg =01001010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-39. timing diagram for globally winning device in block number 3
cynse70256 document #: 38-02035 rev. *e page 59 of 109 cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z a b a b a b a b dq d1 d2 d3 d4 (miss on this device.) (miss on this device.) (miss on this device.) (miss on this device.) cfg =01001010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the b oolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?o r? of lho[0] and lho[1]. figure 10-40. timing diagram for devices below the winning device in block number 3 except device 14 (the last device)
cynse70256 document #: 38-02035 rev. *e page 60 of 109 the following is the sequence of operation for a single 14 4-bit search command (also refer to ?command and command parameters,? section 10.2 on page 19). ? cycle a : the host asic drives cmdv high and applies search comm and code (10) on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[ 8:6] signals must be driven with the bits that will be driven on sadr[23:21] by th is device if it has a hit. dq[71:0] must be driven with the 72-bit data ([143:7 2]) in order to be compared against all even locations . the cmd[2] signal must be driven to logic 0. ? cycle b : the host asic continues to drive cmdv high and to app ly search command code (10) on cmd[1:0]. cmd[5:2] must be driven by the index of the compar and register pair for storin g the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see page 14 for the description of ssr[0:7]). the dq[71:0] is driven with 72-bit data ([71:0]) to be compared against all odd locations. the logical 144-bit search operation is shown in figure 10-42 . the entire table of fifteen devi ces (consisting of 144-bit entries) is compared against a 144-bit word k that is presented on the dq bus in cycles a and b of the command using the gmr and local mask bits. the gmr is the 144-bit word specified by the even and odd global mask pair selected by the gmr index in the command?s cycle a. cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] search2 search4 we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 search4 01 01 01 01 search1 search3 a b a b a b a b z 0 0 |lho[1:0] 0 (global miss; this device is default driver.) i(bhi[2:0]) 0 search3 (hit on some device above.) |(lhi[6:0]) 0 bho[2:0] 0 z 0 0 0 z 1 z 1 0 0 z z 0 1 a b a b a b a b dq d1 d2 d3 d4 (hit on some device above.) (hit on some device above.) cfg =01001010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-41. timing diagram for device number 2 in block number 3 (device 14 in a depth-cascaded table)
cynse70256 document #: 38-02035 rev. *e page 61 of 109 the 144-bit word k that is presented on th e dq bus in cycles a and b of the command is also stored in the even and odd comparand registers specif ied by the comparand register index in command cycle b. in 144 configurations , the even and odd comparand registers can subsequently be used by the learn command in only the first non-full device. [18, 19] the search command is a pipelined operation. it executes a search at half the rate of the frequency of clk2x for 144-bit search es in 144-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 144- bit search command cycle (two clk2x cycles) is shown in table 10-20 . search latency from command to the sram access cycle is 6 for 1?15 devices in the table and tlsz = 10. in addition, ssv and ssf shift further to the right for differ ent values of hlat, as specified in table 10-21 . 10.6.5 288-bit search on 288- configured tables using up to four cynse70256 devices the hardware diagram of t he search subsystem of four devices is shown in figure 10-43 . the following are the parameters programmed into the four devices. ? first seven devices (devices 0?6, bank 0 and 1): cfg = 1010101010101010, tlsz = 01, hlat = 000, lram = 0, and ldev = 0. ? fourth device (device 7, bank 0): cfg = 1010101010101010, tlsz = 01, hlat = 000, lram = 0, and ldev = 0 . ? fourth device (device 7, bank 1): cfg = 1010101010101010, tlsz = 01, hlat = 000, lram = 1, and ldev = 1. [20] notes: 18. the learn command is supported for only one of the blocks consis ting of up to four devices in a depth-cascaded table of more than one block. the word k that is presented on the dq bus in cycles a and b of the command is compared with each entry in the table, starting at location 0. t he first matching entry?s location address l is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see section 12.0, ?sram add ressing,? on page 86). the global winning device will drive the bus in a specific cycle. on global miss cycles th e device with lram = 1 (the default drivi ng device for the sram bus) and ldev = 1 (the default driving device for ssf and ssv signal s) will be the default driver for such missed cycles. 19. during 144-bit searches of 144-bit-configured tables, the search hit will always be at an even address. 20. all four devices must be programmed with the same values of tlsz and hlat. only the last bank of the last device in the tabl e must be programmed with lram = 1 and ldev = 1 (device number 3 in this case). table 10-20. search latency from instruction to sram access cycle number of devices max table size latency in clk cycles 1?4 (tlsz = 01) 256k 144 bits 5 1?14 (tlsz = 10) 960k 144 bits 6 table 10-21. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 0101010101010101 143 0 location 0 2 4 6 1966078 (144-bit configuration) address k gmr comparand register (odd) comparand register (even) a b 143 0 71 0 (first matching entry) l a b even odd will be same in each of banks of each the 15 devices must be same in each bank of each of the 15 devices figure 10-42. 144 ta ble with fifteen devices
cynse70256 document #: 38-02035 rev. *e page 62 of 109 figure 10-44 shows the timing diagram for a search command in the 288- bit-configured table of four devices for device number 0. figure 10-45 shows the timing diagram for a search command in the 288- bit-configured table of four devices for device number 1. figure 10-46 shows the timing diagram for a search command in the 28 8-bit-configured table of four devices for device number 3 (the last device in this table). in these timing diagrams, th ree 288-bit searches are performed sequentially. the hit/miss assu mp- tions were made as shown in table 10-22 . table 10-22. hit/miss assumptions search number 1 2 3 device 0 hit miss miss device 1 miss hit miss devices 2?6 miss miss miss device 7 miss miss miss lho[0] 0123456 lhi lho[0] 01 34 56 lhi lho[1] 0123 456 lhi lho[0] 012345 6 lhi lho[0] lho[1] lho[1] lho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram cynse70256 #0 cynse70256 #1 cynse70256 #2 cynse70256 #3 2 bho[2] cmdv cmd[10:0] ssf, ssv figure 10-43. hardware diagra m for a table with four devices
cynse70256 document #: 38-02035 rev. *e page 63 of 109 cycle clk2x cmdv ce_l oe_l (this device we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ale_l search1 search2 search3 a1 z z z z z z z 0 is the global winner.) |(lhi[6:0]) 0 (miss on this device.) |lho[1:0] cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 z z 0 1 ssv z z 1 ssf z 1z (miss on this device.) cfg = 0101010101010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the b oolean ?or? of the entire bus lhi[6:0]. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-44. timing diagram for 288-bit search device number 0
cynse70256 document #: 38-02035 rev. *e page 64 of 109 cycle clk2x ce_l oe_l (miss on we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 a2 z z z z 1 1 z z |(lhi[6:0]) |lho[1:0] z 0 z 1 z this device.) (this device global winner.) cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 z z 0 search3 (miss on this device.) cfg = 0101010101010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the boolean ?or? of the entire bus lhi[6:0]. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-45. timing diagram for 288-bit search device number 1
cynse70256 document #: 38-02035 rev. *e page 65 of 109 the following is the sequence of operation for a single 288- bit search command (see also subsection 10.2, ?commands and command parameters,? on page 19). ? cycle a : the host asic drives cmdv high and applies search comm and code (10) on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [287:144] of the data be ing searched in this operation. dq[71:0] must be driven with the 72-bit data ([287:216]) to be compared against all locations 0 in the four-word 72-bit page. the cmd[2] signal must be driven to logic 1. [21] ? cycle b : the host asic continues to drive cmdv high and applies search command code (10) on cmd[1:0]. the dq[71:0] is driven with the 72-bit data ([215:1 44]) to be compared against all locations 1 in the four 72-bits-word pages. ? cycle c : the host asic drives cmdv high and applies search comm and code (10) on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [143:0] of the data being se arched. cmd[8:6] signals must be driven with the bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven with the 72-b it data ([143:72]) to be compared against all locations 2 in the fo ur 72-bits-word page. the cmd[2] signal must be driven to logic 0. ? cycle d : the host asic continues to drive cmdv high and appl ies search command code (10) on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing th e address of the matching entry and the hit fl ag (see page 14 for the description of ssr[0:7]). the dq[71:0] is driv en with the 72-bit data ([71:0]) to be compared to all locat ions 3 in the four 72-bits-word pages. cmd[5: 2] is ignored because the learn instru ction is not supported for 288 tables. [22] the logical 288-bit search operation is shown in figure 10-47 . the entire table of 288-bit entries is compared to a 288-bit word k that is presented on the dq bus in cy cles a, b, c, and d of the command usin g the gmr and the local mask bits. the gmr is the 288-bit word specified by the two pair s of gmrs selected by the gmr indexes in command cycles a and c in each of the four devices. the 288-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command is compared to each entry in the table starting at location 0. the first matching entry?s location addr ess l is the winning address that is driven as part of the sram address on the sadr[23:0] lines (s ection 12.0, ?sram addressing,? on page 86). [23] notes: 21. cmd[2] = 1 signals that the search is a 288- bit search. cmd[8:3] in this cycle is ignored. 22. for 288-bit searches, the host asic must supply four distinct 72-bit data words on dq[71:0] during cycles a, b, c, and d. th e gmr index in cycle a selects a pair of gmrs in each of the banks of each of the four devices that ap ply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs in each of the banks of each of the four devices that apply to dq data in cycles c and d. cyc l e clk2x cmdv ce_l oe_l (miss on 1 cyc l e 2 cyc l e 3 cyc l e 4 cyc l e 5 cyc l e 6 cyc l e 7 cyc l e 8 cyc l e 9 cyc l e 10 phs_l sadr[23:0] ssf ssv search1 search2 search3 0 (global miss.) |(lhi[6:0]) |lho[1:0] this device.) 0 z 0 ale_l we_l 1z 1 0 z 1 0 0 z 0 cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 z 0 0 z z 1 z z 0 0 z 0 (miss on this device.) cfg = 0101010101010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0. note: |(lhi[6:0]) stands for the boo lean ?or? of the entire bus lhi[6:0]. note: |lho[1:0] is logical ?o r? of lho[0] and lho[1]. fi g ure 10-46. timin g dia g ram for 288-bit search device number 3 ( last device )
cynse70256 document #: 38-02035 rev. *e page 66 of 109 the search command is a pipelined operation and executes a sear ch at one-fourth the rate of the frequency of clk2x for 288- bit searches in 288-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 288-bit search command (measured in clk cycles) from the clk2x cycle that contains the c and d cycles is shown in table 10-23 . search latency from command to sram ac cess cycle is 5 for only a single device in t he table and tlsz = 01. in addition, ssv and ssf shift further to the right for di fferent values of hlat, as specified in table 10-24 . 10.6.6 288-bit search on tables configured as 288 using up to fifteen cynse70256 devices the hardware diagram of the search subsystem of fifteen devices is shown in figure 10-48 . each of the four blocks in the diagram represents a block of four cynse70256 devices except the last, which has three devices.the diagram for a block of four devices is shown in figure 10-49 . the following are the parameters pr ogrammed into the fifteen devices. ? first thirty devices (devices 0?13, banks 0 and 1): cf g = 1010101010101010, tlsz = 10, hlat = 000, lram = 0, and ldev = 0. ? thirty-first device (device 30, bank 0): cfg = 1010101010101010, tlsz = 10, hlat = 000, lram = 0, and ldev = 0 . ? thirty-first device (device 30, bank 1): cfg = 1010101010101010, tlsz = 10, hlat = 000, lram = 1, and ldev = 1 . [24] note: 23. the matching address is always going to be location 0 in a four-entry page for 288-bit search (two lsbs of the matching inde x will be 00). 24. all fifteen devices must be programmed with the same value for tlsz and hlat. only the last bank in the last device in the t able must be programmed with lram = 1 and ldev = 1 (device number 14 in this case). table 10-23. search latency from instruction to sram access cycle number of devices max table size latency in clk dycles 1?4 (tlsz = 01) 128k 288 bits 5 1?15 (tlsz = 10) 480k 288 bits 6 table 10-24. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 cfg = 1010101010101010 287 0 location 0 4 8 12 524,284 (288-bit configuration) address k gmr 287 0 (first matching entry) l a b 01 c d 23 must be same in each of banks of each of the four devices figure 10-47. 288 table with four devices
cynse70256 document #: 38-02035 rev. *e page 67 of 109 the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 10-25 . for the purpose of illustrating the timings, it is further assumed that there is only one devi ce with the matching entry in each block. figure 10-50 shows the timing diagram for a search command in the 288-bit-conf igured table of fifteen devices for each of the four devices i n block number 0. figure 10-51 shows the timing diagram for a search command in the 288-bit-configured table of fifteen devices for all devices above the winning device in block number 1. figure 10-52 shows the timing diagram for the globally winning device (the final winner within its own and all blocks) in block number 1. figure 10-53 shows the timing diagram for the devices below the globally winning device in block number 1. figure 10-54 , figure 10-55 , and figure 10-56 , respectively, show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winn ing device in block number 2. figure 10-57 , figure 10-58 , figure 10-59 , and figure 10-60 , respectively, show the timing diagrams of the devices above the globally winning device, the globally winning device, the devices below the globally winning device (except device 14), and the last device (device 14) in block number 3. the 288-bit search operation is pipelined a nd executes as follows. four cycles from th e last cycle of the search command, each of the devices knows the outcome internal to it for that operation. in the fifth cycl e from the search command, the devices in a block (less than or equal to four devices resolving the wi nner among them using lhi[6:0] an d lho[1:0] signalling mechanisms) arbitrate for a winner. in the sixth cycle after the search comm and, the blocks of devices resolve the winning block through bhi[2:0] and bho[2:0] si gnalling mechanisms. the winning device within the winning block is the global winning device for the search operation. table 10-25. hit/miss assumptions search number 1 2 3 block 0 missmissmiss block 1 miss miss hit block 2 miss hit hit block 3 hit hit miss bho[2] block of 8 cynse70256s block 0 bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70256s block 3 bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70256s block 1 block of 8 cynse70256s block 2 dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv (devices 0?3) (devices 4?7) (devices 8?11) (devices 12?14) figure 10-48. hardware diagram for a table with fifteen devices
cynse70256 document #: 38-02035 rev. *e page 68 of 109 lho[0] 0123456 lhi lho[0] 01 34 56 lhi lho[1] 0123 456 lhi lho[0] 012345 6 lhi lho[0] lho[1] lho[1] lho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram cynse70256 #0 cynse70256 #1 cynse70256 #2 cynse70256 #3 2 bho[2] cmdv cmd[10:0] ssf, ssv figure 10-49. hardware diagram for a block of up to four devices
cynse70256 document #: 38-02035 rev. *e page 69 of 109 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boole an ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 (miss on this device.) search3 |(lhi[6:0]) 0 bho[2:0] 0 cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) (miss on this device.) figure 10-50. timing diagra m for each device in block number 0 (miss on each device)
cynse70256 document #: 38-02035 rev. *e page 70 of 109 cyc l e clk2x ce_l oe_l we_l 1 cyc l e 2 cyc l e 3 cyc l e 4 cyc l e 5 cyc l e 6 cyc l e 7 cyc l e 8 cyc l e 9 cyc l e 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z z ilho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) (miss on this device.) (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands fo r the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-51. timing diagram for each device above the winning device in block number 1
cynse70256 document #: 38-02035 rev. *e page 71 of 109 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 (this device is global winner.) |(lhi[6:0]) 0 bho[2:0] 0 a3 cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 0 0 1 1 1 (miss on this device.) (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-52. timing diagram for globally winning device in block number 1
cynse70256 document #: 38-02035 rev. *e page 72 of 109 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 0 (miss on this device.) (miss on this device.) (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?o r? of lho[0] and lho[1]. figure 10-53. timing diagram for devices below the winning device in block number 1
cynse70256 document #: 38-02035 rev. *e page 73 of 109 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) (miss on this device.) (miss on this device; hit in block 0 or block 1.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands fo r the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-54. timing diagram for devices ab ove the winning device in block number 2
cynse70256 document #: 38-02035 rev. *e page 74 of 109 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z |lho[1:0] 0 (global winner.) i(bhi[2:0]) 0 (miss on this device.) search3 (hit but not winner.) |(lhi[6:0]) 0 bho[2:0] 0 a2 0 1 1 1 z z z z z z cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 z 0 z z z cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the bool ean ?or? for the enti re bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-55. timing diagram for globally winning device in block number 2
cynse70256 document #: 38-02035 rev. *e page 75 of 109 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 (miss on this device.) search3 |(lhi[6:0]) 0 bho[2:0] 0 z cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands fo r the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-56. timing diagram for devices below the winning device in block number 2
cynse70256 document #: 38-02035 rev. *e page 76 of 109 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) (miss on this device.) (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands fo r the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-57. timing diagram for devices ab ove the winning device in block number 3
cynse70256 document #: 38-02035 rev. *e page 77 of 109 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search2 z z z z z z |lho[1:0] 0 (hit but not global winner.) i(bhi[2:0]) 0 (global winner.) (miss on this device.) |(lhi[6:0]) 0 bho[2:0] 0 a1 0 z 1 1 1 z z z z z cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 0 z search1 search3 cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the bool ean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-58. timing diagram for globally winning device in block number 3
cynse70256 document #: 38-02035 rev. *e page 78 of 109 cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 z z z z z z |lho[1:0] 0 i(bhi[2:0]) 0 search3 |(lhi[6:0]) 0 bho[2:0] 0 z cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 (miss on this device.) (miss on this device.) (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boolean ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boole an ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-59. timing diagra m for devices below the winning device in block number 3 except device 14 (last device)
cynse70256 document #: 38-02035 rev. *e page 79 of 109 the following is the sequence of operation for a single 288- bit search command (see also subsection 10.2, ?commands and command parameters,? on page 19). ? cycle a : the host asic drives cmdv high and applies search comm and code (10) on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [287:144] of the data bein g searched. dq[71:0] must be driven with the 72-bit data ([287:216]) to be compared to all lo cations 0 in the four 72-bits-word page. the cmd[2] signal must be driven to logic 1. [25] ? cycle b : the host asic continues to drive cmdv high and to app ly search command (10) on cmd[1:0]. the dq[71:0] is driven with the 72-bit data ([215: 144]) to be compared to all locations 1 in the four 72-bits-word pages. ? cycle c : the host asic drives cmdv high and applies search comm and code (10) on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to t he gmr pair used for the bits [143:0] of the data being searched. cmd[8:6] signals must be driven with the bits that will be dr iven by this device on sadr[23:21] if it has a hit. dq[71:0] must be driven with th e 72-bit data ([143:72]) to be compared to all locations 2 in the four 72-bits-word pages. the cm d[2] signal must be driven to logic 0. note: 25. cmd[2] = 1 signals that the search is a 288-bit search. cmd[8:6] is ignored in this cycle. cycle clk2x ce_l oe_l we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv ale_l search1 search2 z 0 0 |(lhi[6:0)] i(bhi[2:0]) 0 (hit on some device above.) search3 0 bho[2:0] 0 z 0 1 cmdv cmd[1:0] cmd[10:2] 01 01 search1 search2 a b a b a b a b cmd[2] a b c d a b c d dq d1 d2 a b c d d3 a b a b 01 search3 |lho[1:0] 0 z z 0 0 0 z 0 z 1 1 z z 0 z 0 0 z 0 z 0 0 z (hit on some device above.) (hit on some device above.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0. note: |(bhi[2:0]) stands for the boole an ?or? of the entire bus bhi[2:0]. note: |(lhi[6:0]) stands for the boolean ?or? for the entire bus lhi[6:0]. note: each bit in bho[2:0] is the same logical signal. note: |lho[1:0] is logical ?or? of lho[0] and lho[1]. figure 10-60. timing diagram of the last devi ce in block number 3 (device 14 in the table)
cynse70256 document #: 38-02035 rev. *e page 80 of 109 ? cycle d : the host asic continues to drive cmdv high and to app ly search command code (10) on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing th e address of the matching entry and the hit fl ag (see page 14 for a description of ssr[0:7]). the dq[71:0] is driv en with the 72-bit data ([71:0]) to be compared to all locatio ns 3 in the four 72-bits-word pages. cmd[5:2] is ignored because the learn instruct ion is not supported for 288 tables. [26] the logical 288-bit search operation is shown in figure 10-61 . the entire table of 288-bit entries is compared to a 288-bit word k that is presented on the dq bus in cycl es a, b, c, and d of the command using the gmr and local mask bits. the gmr is the 288-bit word specified by the two pairs of gmrs selected by the gmr indexes in comm and cycles a and c in ea ch of the fifteen devices. the 288-bit word k that is presented on the dq bus in c ycles a, b, c, and d of the command is compared to each entry in the table starting at location 0. the first matching entry?s location address l is the winning address that is driven as par t of the sram address on the sadr[23:0] lines (see ?sram addressing? on page 86). [27] the search command is a pipelined operation and executes a sear ch at one-fourth the rate of the frequency of clk2x for 288- bit searches in 288-configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 288-bit search command (measured in clk cycles) from the clk2x cycle that contains the c and d cycles is shown in table 10-26 . search latency from command to sram acce ss cycle is 6 for a single device in the table and tlsz = 10. in addition, ssv and ssf shift further to the right for differ ent values of hlat, as specified in table 10-27 . table 10-26. search latency from instruction to sram access cycle number of devices max table size latency in clk cycles 1?8 (tlsz = 01) 128k 288 bits 5 1?15 (tlsz = 10) 480k 288 bits 6 table 10-27. shift of ssf and ssv from sadr hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 notes: 26. for 288-bit searches, the host asic must supply four distinct 72-bit data words on dq[71:0] during cycles a, b, c, and d. th e gmr index in cycle a selects a pair of gmrs in each of the fifteen devices that apply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs in each of the fifteen devices that apply to dq data in cycles c and d. 27. the matching address is always going to be location 0 in a f our-entry page for 288-bit search (two lsbs of the matching inde x will be 00). cfg = 1010101010101010 287 0 location 0 4 8 12 1,966,076 (288-bit configuration) address k gmr 287 0 (first matching entry) l a b 01 c d 23 must be same in each of the 15 devices figure 10-61. 288 ta ble with fifteen devices
cynse70256 document #: 38-02035 rev. *e page 81 of 109 10.6.7 mixed-size searches on tables configured with different widths using a cynse70256 with cfg_l low this subsection will cover mixed searches (72, 144, and 288) wi th tables of different widths (72, 144, 288). the sample operation shown is for a single device with cfg = 1010010100000000 that contains three tables of 72, 144, and 288 widths. the operation can be generalized to a block of 4?15 devices usin g four blocks; the timing and pipeline operation is the same as described previously for fixed searches on a table of one-width size. figure 10-62 shows three sequential searches: first, a 72-bit sear ch on a 72-configured table; a 144-bit search on a 144- configured table; finally, a 288-bit search on a 288-configured table that each results in a hit. [28] figure 10-63 shows the sample table. two bits in each 72-bit entry will need to designated as the table number bits. one choice can be the 00 values for the table configured as 72, 01 values for tables configured as 144, and 10 values for tables configur ed as 288. for the above explanation , it is further assumed that bits [71:70] for each entry will be designed as such table designation bits. note: 28. the dq[71:70] will be 00 in each of the two a and b cycles of the 72-bit search (search1). dq[71:70] is 01 in each of the a and b cycles of the 144-bit search (search2). dq[71:70] is 10 in each of the a, b, c, and d cycles of the 288-bit search (search3). by having table designation b its, the cynse70256 device enables the creation of many tables in a bank of nses of different widths. cycle clk2x cmdv cmd[1:0] ce_l oe_l cmd[10:2] we_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cfg = 1010010100000000, hlat = 010, tlsz = 00, lram = 1, ldev = 1. phs_l sadr[23:0] ssf ssv ale_l a2 01 01 search1 search3 a b a b a b a b 0 1 0 10 0 1 1 0 1 0 ab a b a b c d dq d1 d3 cmd[2] 101 1 0 1 a3 search2 01 d2 1 1 0 0 0 a1 a3 search1 search2 0 1 0 1 x72 hit x144 hit search2 x288 hit figure 10-62. timing diagram for mixed search (one device) 4k 32k 72 8k 144 288 cfg = 1010010100000000 figure 10-63. multiwidth configurations example
cynse70256 document #: 38-02035 rev. *e page 82 of 109 10.6.8 mixed-size searches on tables configured to diffe rent widths using a cynse7 0256 device with cfg_l high this subsection will cover the mixed-size searches (72, 144 and 288) with tables of different widths (72, 144, 288) with cfg_l set high. the previous subsection described searches on t ables of different widths using table designation bits in the data array, which can be wasteful. in order to avoid the waste of these bits and yet support up to three tables of 72, 144 an d 288 widths, cmd[2] and cmd[9] (in cfg_l high mode) in cycle a of the command can be used as shown in table 10-28 . 10.7 lram and ldev description when nses are cascaded using multiple cynse70256 devices, the sadr, ce_l, and we_l (three-state signals) are all tied together. in order to eliminate external pull-up and pull dow ns, one device in a bank is desi gnated the default driver. for non search or nonlearn cycles (see subsec tion 10.8, ?learn command?) or search cycles with a global miss, the sadr, ce_l, and we_l signals are driven by the device with the lr am bit set. it is important that only one device in a bank of cascaded nses have th is bit set. failure to do so will cause contention on the sadr, ce _l, and we_l, and can potentially cause damage to the device(s). similarly, when nses using multiple cynse70256 devices ar e cascaded, ssf and ssv (also three-state signals) are tied together. in order to eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. for nonsearch cycles or search cycles with a global miss, the ssf and ssv signals are driven by the device with the ldev bit set in bank 1. it is important that only one device in a bank of ca scaded nses have this bit set. failure to do so will cause conte ntion on the ssv and ssf, and can potentiall y cause damage to the device(s). 10.8 learn command bit[0] of each 72-bit data location spec ifies whether an entry in the database is o ccupied. if all the entries in a device are occupied, the device asserts a fulo signal to inform the downstream devices th at it is full. the result of this communication between dep th- cascaded devices determines the global full signal for the ent ire table. the full signal in the last device determines the fullness of the depth-cascaded table. the device contains sixteen pairs of internal 72-bit-wide compar and registers that store the co mparands as the device executes searches. on a miss by the search that is signalled to the asic through the ssv and ssf signals (ssv = 1, ssf = 0), the host asic can apply the learn command to learn the entry from a comp arand register as to the next -free location (see subsection 7.8, ?nfa register,? on page 17). the nfa register is updated with the new next-free location information following each write or learn command. in a depth- cascaded table, only a single device will learn the entry through the application of a learn instruction. the determination as to which device will learn is based on the fuli and fulo signals between the devices. the first non-full device learns the entry by storing the contents of the specified co mparand registers to the location(s) pointed to by the nfa register. in a 72-configu red table, the learn command writes a single 72-bit location. in a 144-configured table, the learn command wr ites the next even and odd 72-bit locations. in 144-bit mode, bi t[0] of the even and odd 72-b it locations is 0, indicating that they are cascaded empty, or 1, indicating that they are occupied. the global full signa l indicates to the table controll er (the host asic) that all entr ies within a block are occupied and that no mo re entries can be learned. the cynse7 0256 device updates the signal after each write or learn command to a data array. the learn command gener ates a write cycle to the external sram, also using the nfa register as part of the sram address (see section 12.0, ?sram addressing,? on page 86). the learn command is supported on a single block containing up to four devices if the table is configured either as 72 or 144 ; it is not supported for 288-configured tables. the learn co mmand is a pipelined operation and lasts for two clk cycles, as shown in figure 10-64 and figure 10-65 where tlsz = 01. figure 10-64 and figure 10-65 assume that the device performing the learn operation is not the la st device in the table and will therefore have its lram bit set to 0. [29] note: 29. the oe_l for the device with the lram bi t set goes high for two cycles for each learn (one during the sram write cycle and o ne during the cycle before). the sram write cycle latency from the sec ond cycle of the instruction is shown in table 10-29 . table 10-28. searches with cfg_l set high cmd[9] cmd[2] search 0 0 search 72-bit-configured partitions only. 1 0 search 144-bit-configured partitions only. x 1 cycles a and b for searching 288-bit-configured partitions. x 0 cycles c and d for searching 288-bit-configured partitions.
cynse70256 document #: 38-02035 rev. *e page 83 of 109 \ table 10-29. sram write cycle latency fr om second cycle of learn instruction number of devices latency in clk cycles 1?4 (tlsz = 01) 5 1?15 (tlsz = 10) 6 cycle learn1 learn2 clk2x cmdv cmd[1:0] dq sadr[23:0] ce_l cmd[10:2] we_l oe_l a1 a2 x xxx x tlsz = 01, lram = 0, ldev = 0. 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 x 1a1b comp1 comp2 x phs_l z z z z z z z 0 0 z z ssv ssf z 0 0 x figure 10-64. timing diagram of learn (except on the last device [tlsz = 01]) cycle learn1 learn2 clk2x cmdv cmd[1:0] dq sadr[23:0] ce_l cmd[10:2] x we_l oe_l x xxx x tlsz = 01, lram = 1, ldev = 1. 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 x x x 1a 1b comp1 comp2 x phs_l 1 1 z z z z z 0 zz zz 0 0 ssv ssf 1 1 1 0 z 1 1 figure 10-65. timing diagram of learn on device number 3 (tlsz = 01)
cynse70256 document #: 38-02035 rev. *e page 84 of 109 the learn operation lasts two clk cycles. the sequence of operation is as follows. ? cycle 1a : the host asic applies the learn instruct ion on cmd[1:0] using cm dv = 1. the cmd[5:2] field specifies the index of the comparand register pair that will be written in the data array in the 144-bit-configured table. for a learn in a 72-bit- configured table, the even-numbered comparan d specified by this index will be written. cmd[8:6] carries the bits that will be driven on sadr[23:21] in the sram write cycle. ? cycle 1b : the host asic continues to drive cmdv to 1, cmd[1:0] to 11, and cmd[5:2] with the comparand pair index. cmd[6] must be set to 0 if the learn is being performed on a 72-bit- configured table, and to 1 if the learn is being performed on a 144-bit-configured table. ? cycle 2 : the host asic drives cmdv to 0. at the end of cycle 2, a new instruction can begin. sram write la tency is the same as the search to the sram read cycle. it is measured from the second cycl e of the learn instruction. 11.0 depth cascading the nse application can depth-cascade the dev ices to various table sizes of different widths (72 bits, 144 bits, or 288 bits). the devices perform all the necessary arbitration to decide which dev ice will drive the sram bus. search latency increases as the table size increases; the search rate itself remains constant. 11.1 depth cascading up to four devices (one block) figure 11-1 shows that up to four devices can be cascaded to form 512k 72, 256k 144, or 128k 288 tables. it also shows the interconnection between devices for depth cascading. each nse asserts the lho[1] and lho[0] signals to inform downstream devices of its result . lhi[6:0] signals for a device are connected to lho signals of the upstream devices. the host asic must program the tlsz to 01 for each of up to four devices in a block. only a single device drives the sram bus in any single cycle. 11.2 depth cascading up to fifteen devices (four blocks) figure 11-2 shows the cascading of up to four blocks. each block except the last c ontains up to four cynse70256 devices, and the interconnection within each with the casc ading of up to four devices in a block was shown in the previous subsection. [30] note: 30. the interconnection between blocks for dep th cascading is important. for each search, a block asserts bho[2], bho[1], and bh o[0]. the bho[2:0] signals for a block are taken only from the last device in that block. fo r all other devices within that block, these signals stay open and floating. the host asic must program tlsz to 10 in each of the devices for cascadin g up to fifteen devices (in up to four blocks). lho[0] 0123456 lhi lho[0] 01 34 56 lhi lho[1] 0123 456 lhi lho[0] 012345 6 lhi lho[0] lho[1] lho[1] lho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram cynse70256 #0 cynse70256 #1 cynse70256 #2 cynse70256 #3 2 bho[2] cmdv cmd[10:0] ssf, ssv figure 11-1. hardware diagram for a block of up to four devices
cynse70256 document #: 38-02035 rev. *e page 85 of 109 11.3 depth cascading for a full signal bit[0] of each of the 72-bit entries is de signated as a special bit (1 = occupied, 0 = empty). for each learn or pio write to t he data array, each device asserts fulo[1] or fulo[0] depending on whether or not it has any empty locations within it (see figure 11-3 ). each device combines the fulo signals from the devices above it with its own full status to generate a full signal that gives the full status of the table up to the device asserting the full signal. figure 11-3 shows the hardware connection diagram for generating the full signal that goes back to the asi c. in a depth-cascaded block of up to four devices, the full signal from the last device should be fed ba ck to the asic controller to indicate the fu llness of the table. the full signal of the other devices should be left open. [31] note: 31. the learn instruction is supported for only up to four devices , whereas full cascading is allowed only for one block in tabl es containing more than four devices. in tables for which a learn instruction is not going to be us ed, the bit[0] of each 72-bit entry should always be set to 1. bho[2] block of 8 cynse70256s block 0 bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70256s block 3 bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70256s block 1 block of 8 cynse70256s block 2 dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv (devices 0?3) (devices 4?7) (devices 8?11) (devices 12?14) figure 11-2. depth cascading four blocks
cynse70256 document #: 38-02035 rev. *e page 86 of 109 12.0 sram addressing table 12-1 describes the commands used to generate addresses on the sram address bus. the index [15:0] field contains the address of a 72-bit entry that results in a hit in 72-bit-config ured quadrant. it is the address of the 72-bit entry that lies at the 144- bit page, and the 288-bit page boundaries in 144-bit- and 288-bit-configured quadrants, respectively. section 7.0, ?registers,? on page 13 of this datasheet describes the nfa and ssr regi sters. adr[15:0] c ontains the address supplied on the dq bus during pio access to the cynse70256. command bits 8, 7, and 6 {cmd[8:6]} are passed from the command to the sram address bus. see sectio n 10.0, ?commands,? on page 19, for more information. id[4:0] is the id of the device driving the sram bus (see section 18.0, ?pinout descr iptions and package diagrams,? on page 103, for more infor- mation). 12.1 sram pio access the remainder of section 12.0 descri bes sram read and write operations. sram read enables read access to the off-chip sram containing associative data. the latency from the issuance of the read instruction to the appearance of the address on the sram bus is the same as the search instruction latency, and will depend on the value programmed for the tlsz parameter in the device co nfiguration register. the latency of the ack from the read instruction is the same as that from t he search instruction to the sram address latency, plus the hlat programmed in the configuration register. [32, 33] notes: 32. sram read is a blocking operation?no new instruction can begin until the ack is returned by the selected device performing t he access. sram write enables write access to the off-chip sram containing associative data. t he latency from the second cycle of the write instruction to th e appearance of the address on the sram bus is the same as the search instruction latency, and will depend on the tlsz value parameter programmed in the devic e configuration register. 33. sram write is a pipelined operation. table 12-1. sram bus address command sram operation 23 22 21 [20:17] 16 [15:0] search read c8 c7 c6 id[4:1] bank index[15:0] learn write c8 c7 c6 id[4:1] bank nfa[15:0] pio read read c8 c7 c6 id[4:1] bank adr16:0] pio write write c8 c7 c6 id[4:1] bank adr[15:0] indirect access write/read c8 c7 c6 id[4:1] bank ssr[15:0] 3 fulo[0] 0123456 fuli fulo[0] 01 34 56 lhi fulo[1] 012 456 lhi fulo[0] 012345 6 fuli fulo[0] fulo[1] fulo[1] fulo[1] full dq[71:0] sram cynse70256 #0 cynse70256 #1 cynse70256 #2 cynse70256 #3 2 cmdv cmd[10:0] ssf, ssv v dd v dd v dd v dd figure 11-3. full signal generation in a cascaded table
cynse70256 document #: 38-02035 rev. *e page 87 of 109 12.2 sram read with a table of up to four devices the following explains the sram read operation completed throu gh a table of up to four devices using the following parameter: tlsz = 01. figure 12-1 diagrams a block of four devices. the followin g assumes that sram access is successfully achieved through cynse70256 device number 0. figure 12-2 and figure 12-3 show timing diagrams for device number 0 and device number 3, respectively. ? cycle 1a : the host asic applies the read instru ction on cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. the host asic selects the de vice for which id[4:0] matches the dq[25:21] lines. during this cycle the host asic also supplies sadr[ 23:21] on cmd[8:6]. ? cycle 1b : the host asic continues to apply the read instruction on cmd[1:0], using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. ? cycle 2 : the host asic floats dq[71:0] to a three-state condition. ? cycle 3 : the host asic keeps dq[71:0] in a three-state condition. ? cycle 4 : the selected device starts to drive dq[71:0]. ? cycle 5 : the selected device continues to drive dq[7 1:0] and drives ack from high-z to low. ? cycle 6 : the selected device drives the read address on sadr [23:0], and drives ack hi gh, ce_l low, we_l high, and ale_l low. ? cycle 7 : the selected device drives ce_l , ale_l, we_l, and the dq bus in a three-state conditi on. it continues to drive ack low. at the end of cycle 7, the selected device floats ack in a three-state condition. a new command can begin. lho[0] 0123456 lhi lho[0] 01 34 56 lhi lho[1] 0123 456 lhi lho[0] 012345 6 lhi lho[0] lho[1] lho[1] lho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram cynse70256 #0 cynse70256 #1 cynse70256 #2 cynse70256 #3 2 bho[2] cmdv cmd[10:0] ssf, ssv figure 12-1. hardware diagram of a block of four devices
cynse70256 document #: 38-02035 rev. *e page 88 of 109 cycle clk2x cmdv cmd[1:0] dq read address oe_l we_l ce_l sadr address 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 01, hlat = 000, lram = 0, ldev = 0 phs_l cmd[10:2] a b z z z z 0 z z z ssv z ssf ale_l z 0 z z 0 0 1 z z 1 cyc l e 7 dq driven by selected cynse70256 figure 12-2. sram read through device number 0 in a block of four devices cycle clk2x cmdv cmd[1:0] dq read address oe_l we_l ce_l sadr 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 tlsz = 01, hlat = 000, lram = 1, ldev = 1 phs_l cmd[10:2] a b z 0 1 z z 1 1 ssv z ssf ale_l 1 z 1 z z z ack z 1 figure 12-3. sram read timing for device number 7 in a block of four devices
cynse70256 document #: 38-02035 rev. *e page 89 of 109 12.3 sram read with a table of up to fifteen devices the following explains the sram read operation accomplished thr ough a table of up to fifteen devices, using the following parameter: tlsz = 10. the hardware diagram is shown in figure 12-4 . the following assumes that sram access is being accomplished through cynse70256 device number 0, a nd that device number 0 is the selected device. figure 12-5 and figure 12-6 show the timing diagrams for device number 0 and device number 14, respectively. ? cycle 1a : the host asic applies the read instru ction to cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. the host asic selects the devi ce for which the id[4:0] matches the dq[25:21] lines. during this cycle, the host asic also supplies sadr[23:21] on cmd[8:6]. ? cycle 1b : the host asic continues to apply the read instruction to cmd[1:0], using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to 10, to select the sram address. ? cycle 2 : the host asic floats dq[71:0] to a three-state condition. ? cycle 3 : the host asic keeps dq[71:0] in a three-state condition. ? cycle 4 : the selected device starts to drive dq[71:0]. ? cycles 5 to 6 : the selected de vice continues to drive dq[71:0]. ? cycle 7 : the selected device continues to drive dq [71:0], and drives an sram read cycle. ? cycle 8 : the selected device drives acl from z to low. ? cycle 9 : the selected device drives ack to high. ? cycle 10 : the selected device drives ack from high to low. at the end of cycle 10, the selected device floats ack in a three-state condition. bho[2] block of 8 cynse70256s block 0 bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70256s block 3 bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70256s block 1 block of 8 cynse70256s block 2 dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv (devices 0?3) (devices 4?7) (devices 8?11) (devices 12?14) figure 12-4. hardware diagram of fifteen devices using four blocks
cynse70256 document #: 38-02035 rev. *e page 90 of 109 12.4 sram write with a table of up to four devices the following explains the sram write operation accomplished through a table(s) of up to fo ur devices with the following parameters ( tlsz = 01). the hardware diagram for this table is shown in figure 12-7 . the following assume s that sram access is achieved through cynse70256 device number 0. figure 12-8 and figure 12-9 show the timing diagram for device number 0 and device number 3, respectively. cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv z z z z cmdv cmd[1:0] cmd[10:2] 00 read a b address dq address 0 z z 1 we_l oe_l z ale_l z 0 z z z z z 1 0 0 ack dq driven by the selected cynse70256 tlsz = 10, hlat = 010, lram = 0, ldev = 0 figure 12-5. sram read through device number 0 in a bank of fifteen devices (device number 0 timing) cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv 1 0 0 cmdv cmd[1:0] cmd[10:2] 00 read a b address dq z 1 we_l oe_l 0 ale_l 1 z 1 z ack z 1 1 z tlsz = 10, hlat = 010, lram = 1, ldev = 1 figure 12-6. sram read through device number 0 in a bank of fifteen devices (device number 14 timing)
cynse70256 document #: 38-02035 rev. *e page 91 of 109 ? cycle 1a : the host asic applies the write instru ction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. the host asic selects the device for which th e id[4:0] matches the dq[25:21] lines. the host asic also supplies sadr[ 23:21] on cmd[8:6] in this cycle. [34] ? cycle 1b : the host asic continues to apply the write instruction on cmd[ 1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. [34] ? cycle 2 : the host asic continues to drive dq [71:0]. the data in this cycle is not used by the cynse70256 device. ? cycle 3 : the host asic continues to drive dq [71:0]. the data in this cycle is not used by the cynse70256 device. at the end of cycle 3, a new command can begin. write is a pi pelined operation, but the writ e cycle appears at the sram bus with the same latency as that of a se arch instruction, as me asured from the second cycle of the write command. note: 34. cmd[2] must be set to 0 for sram write because burst writes into the sram are not supported. lho[0] 0123456 lhi lho[0] 01 34 56 lhi lho[1] 0123 456 lhi lho[0] 012345 6 lhi lho[0] lho[1] lho[1] lho[1] bho[0] bho[1] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] dq[71:0] sram cynse70256 #0 cynse70256 #1 cynse70256 #2 cynse70256 #3 2 bho[2] cmdv cmd[10:0] ssf, ssv figure 12-7. hardware diagram of a block of four devices cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv z z z cmdv cmd[1:0] cmd[10:2] 01 write a b address dq address 0 we_l oe_l z ale_l z z z ack x x z z z 0 z z 0 z tlsz = 01, hlat = xxx, lram = 0, ldev = 0 figure 12-8. sram write through device number 0 in a block of four devices
cynse70256 document #: 38-02035 rev. *e page 92 of 109 12.5 sram write with table(s) consisting of up to fifteen devices the following explains the sram write operation accomplished through a table of up to fifteen devices with the following parameter: tlsz = 10. the hard ware diagram is shown in figure 12-10 . the following assumes that sram access is accom- plished through the selected device: cynse70256 device number 0. figure 12-11 and figure 12-12 show timing diagrams for device number 0 and device number 14, respectively. ? cycle 1a : the host asic applies the write instru ction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. the host asic selects the device for which th e id[4:0] matches the dq[25:21] lines. the host asic also supplies sadr[ 23:21] on cmd[8:6] in this cycle. [34] ? cycle 1b : the host asic continues to apply the write instruction on cmd[ 1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to 10 to select the sram address. [34] ? cycle 2 : the host asic continues to drive dq [71:0]. the data in this cycle is not used by the cynse70256 device. ? cycle 3 : the host asic continues to drive dq [71:0]. the data in this cycle is not used by the cynse70256 device. at the end of cycle 3, a new co mmand can begin. the write is a pipelined operation, but the write cycle appears at the sram bus with the same latency as that of a search instructi on, as measured from the se cond cycle of the write command. cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv 1 0 0 cmdv cmd[1:0] cmd[10:2] 01 write a b address dq z we_l oe_l 0 ale_l z z ack x x 1 0 1 1 z 1 1 z 1 tlsz = 01, hlat = xxx, lram = 1, ldev = 1 figure 12-9. sram write timing for devi ce number 3 in block of four devices
cynse70256 document #: 38-02035 rev. *e page 93 of 109 bho[2] block of 8 cynse70256s block 0 bho[1] bho[0] bhi[2] bhi[1] bhi[0] bhi[2] block of 7 cynse70256s block 3 bhi[1] bhi[0] gnd bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] gnd bhi[2] bhi[1] bhi[0] gnd block of 8 cynse70256s block 1 block of 8 cynse70256s block 2 dq[71:0] sram bho[2] bho[2] bho[1] bho[1] bho[0] bho[0] cmd[10:0], cmdv ssf, ssv (devices 0?3) (devices 4?7) (devices 8?11) (devices 12?14) figure 12-10. table of fi fteen devices (four blocks) cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv z z z cmdv cmd[1:0] cmd[10:2] 01 write a b address dq address 0 we_l oe_l z ale_l z z z ack x x z z z 0 z z 0 z tlsz = 10, hlat = xxx, lram = 0, ldev = 0 figure 12-11. sram write through device number 0 in bank of fifteen devices (device 0 timing)
cynse70256 document #: 38-02035 rev. *e page 94 of 109 13.0 power cynse70256 has two separate power supplies, one for the core (v dd ) and another for the ios (v ddq ). 13.1 power-up sequence proper power-up sequence is required to correctly initialize the cy press network search engines before functional access to the device can begin. rst_l and trst_l should be held low before th e power supplies ramp up. rst_l must be set low for a duration of time afterward and then set high. the following steps describe the proper power-up sequence. 1. set rst_l and trst_l low. 2. power up v dd , v ddq and start running clk1x when operating in clk1x mode or clk2x and phs_l when operating in clk2x mode. the order in which these signals (including v dd and v ddq ) are applied is not critical. 3. rst_l should be held low for 0.5 ms (pll lock time requirement) . in clk1x mode, the counting starts on the first rising edge of clk1x after both v dd and v ddq have reached their steady state voltages. in clk2x mode, the counting starts on the first rising edge of clk2x when phs_l is high, after both v dd and v ddq have reached their steady state voltages. 4. continue to hold rst_l low for a minimum of 32 clk1x cycles (when operating in clk1x mode) or 64 clk2x cycles (when operating in clk2x mode). set rst_l to high afterward to co mplete the power-up sequence. for jtag reset, trst_l can be brought high after v dd and v ddq have both reached their steady state voltages. 0 0 z cycle clk2x ce_l 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 phs_l sadr[23:0] ssf ssv 1 cmdv cmd[1:0] cmd[10:2] 01 write a b address dq z we_l oe_l 0 ale_l z ack x x 1 1 1 z 1 1 z 1 tlsz = 10, hlat = xxx, lram = 1, ldev = 1 figure 12-12. sram write through device nu mber 0 in bank of fifteen cynse70256 devices (device number 14 timing)
cynse70256 document #: 38-02035 rev. *e page 95 of 109 figure 13-1 and figure 13-2 illustrate the proper sequences of the power-up operation. 13.2 power consumption the following figure depicts expected power consumption over a range of frequencies. the calc ulations assume 100% of the operations will be search operations. if an application includes other operations such as read or write, then power consumption will be lower. the worst case line indicates power c onsumption when the i/os switch 100 percent of the time. the other lines (all search hit and all search mi ss) assume the i/os swit ch 50% of the time. figure 13-1. power-up sequence (clk2x) figure 13-2. power-up sequence (clk1x) vdd vddq 64 clk2x clk2x phs_l rst_l trst_l cycles pll lock time, 0.5ms vdd vddq pll lock time, 0.5ms 64 clk2x clk1x rst_l trst_l cycles
cynse70256 document #: 38-02035 rev. *e page 96 of 109 figure 13-3. power consumption of cynse70256 14.0 application figure 14-1 shows how an nse subsystem can be formed using a host asic and a cynse70256 b ank. it also shows how this nse subsystem is integrated in a switch or router. the cynse70256 device can access synchronous and asynchronous srams by allowing the host asic to set the same hlat parameter in all nses within a bank of nses. 15.0 jtag (1149.1) testing the cynse70256 device supports the test access port and bound ary scan architecture as specified in ieee jtag standard number 1149.1. the pin interface to the chip consists of five signals with the standard definitions: tck, tms, tdi, tdo, and trst_l. table 15-1 describes the operations that the test access port controller supports, and ta ble 15 -2 describes the tap pow er consum ption of cynse70256 0 2 4 6 8 10 12 14 0 102030405060708090 frequency (m hz) power (w) a ll i/o sw itching (75c) a ll search hit (75c) a ll search miss (75c) p r o g r a m m e m o r y n e t w o r k l i n e i n t e r f a c e s s y s t e m b u s s w i t c h p r o c e s s o r s w i t c h f a b r i c h o s t a s i c s r a m b a n k nse figure 14-1. sample switch/router using the cynse70256 device
cynse70256 document #: 38-02035 rev. *e page 97 of 109 device id register. [35] note : to disable jtag functionality, connect the tck, tms and tdi pins to vddq through a pull-up, and trst_l to ground through a pull-down 16.0 electrical specifications this section describes the electrical spec ifications, capacitance, operating conditions, dc characteristics, and ac timing para m- eters for the cynse70256 device (see table 16-1 and table 16-2 ). table 15-1. supported operations instruction type description sample/preloa d mandatory sample/preload . this operation loads the values of si gnals going to and from i/o pins into the boundary scan shift register to provide a snapshot of the normal functional operation. extest mandatory external test . this operation uses boundary scan values shifted in from the tap to test connec- tivity external to the device. bypass mandatory bypass . this operation bypasses the device in a jtag chain by loading a single bit shift register between tdi and tdo and provides a minimum-le ngth serial path when no test operation is required. idcode optional device jtag id code . this operation selects the jtag id entification register and output the idcode field serially through tdo. clamp optional output clamp . this operation drives preset values onto the outputs of the device. highz optional high-z output . this operation sets the device output signals in high impedance state. table 15-2. tap device id register field range initial value description revision [31:28] 0001 revision number . this is the current device revision number. numbers start from one and increment by one for each revision of the device. part number [27:12] 0000 0000 0000 0100 th is is the part number for the device. mfid [11:1] 000_1101_1100 manufacturer id . this field is the same as the manufacturer id used in the tap controller. lsb [0] 1 least significant bit. note: 35. to disable jtag functionality, connect the tck, tms, and tdi pins tovddq through a pull-up, and trst_l to ground through a p ull-down. table 16-1. dc electrical ch aracteristics for cynse70256 parameter description conditions min. max. unit i li input leakage current v ddq = v ddq max, v in = 0 to v ddq max ?20 20 a i lo output leakage current v ddq = v ddq max, v in =0 to v ddq max ?20 20 a v il input low voltage (2.5v) ?0.3 0.7 v v ih input high voltage (2.5v) 1.7 v ddq + 0.3 v v ol output low voltage (2.5v) v ddq = v ddq min, i ol = 8ma 0.4 v v oh output high voltage (2.5v) v ddq = v ddq min, i oh = 8ma 2.0 v v il input low voltage (3.3v) -0.3 0.8 v ih input high voltage (3.3v) 2.0 v ddq + 0.3 v ol output low voltage (3.3v) v ddq = v ddq min, i ol = 8ma 0.4 v v oh output high voltage (3.3v) v ddq = v ddq min, i oh = 8ma 2.4 v i dd2 3.3v/2.5v supply current at v dd max 83-mhz search rate, l out = 0ma 600 ma i dd2 3.3v/2.5v supply current at v dd max 66-mhz search rate, l out = 0ma 480 ma i ddl 1.5v supply current at v dd (typical) 83-mhz search rate 7.4 [41] a i ddl 1.5v supply current at v dd (typical) 66-mhz search rate 5.9 [41] a
cynse70256 document #: 38-02035 rev. *e page 98 of 109 parameter description max. unit c in input capacitance 12 pf [36] c out output capacitance 12 pf [37] table 16-2. operating conditions for cynse70256 parameter description min. max. unit v ddq = 3.3v operating volt age for i/o 3.135 3.465 v v ddq = 2.5v operating volt age for i/o 2.375 2.625 v v dd operating supply voltage 1.425 1.575 v v ih input high voltage [39] (2.5v) 1.7 v ddq + 0.3 v v il input low voltage [38] (2.5v) ?0.3 0.7 v v ih input high voltage [40] (3.3v) 2.0 v ddq + 0.3 v v il input low voltage [38] (3.3v) ?0.3 0.8 v t a ambient operating temperature 0 70 c t j junction temperature 0 150 [42] c supply voltage tolerance ?5% +5% notes: 36. f = 1 mhz, v in = 0 v. 37. f = 1 mhz, v out = 0 v. 38. minimum allowable applies to undershoot only. 39. maximum allowable applies to overshoot only (v ddq is 2.5v supply). 40. maximum allowable applies to overshoot only (v ddq is 3.3v supply). 41. typical. 80% compare utilization. 42. please refer to ?cynse70256 airflow and h eat sink requirements? application note.
cynse70256 document #: 38-02035 rev. *e page 99 of 109 17.0 ac timing waveforms table 17-1 and ta ble 17 -2 show the ac timing parameters for the cynse70256 device. table 17-3 shows the ac test conditions for the cynse70256 device. figure 17-1 shows the input wave form for the cynse70256 device. figure 17-2 and figure 17-3 show the output load and output load equivalent of the cynse70256 device. figure 17-4 shows timing wave form diagrams for clk2x. figure 17-5 details timing wave form diagrams for clk1x. table 17-1. ac timing parameters with clk2x parameter description cynse70256-066 cynse70256-083 unit min. max. min. max. f clock clk2x frequency. 40 133 40 166 mhz t clok pll lock time. 0.5 0.5 ms t ckhi clk2x high pulse. [43] 3.0 2.4 ns t cklo clk2x low pulse. [43] 3.0 2.4 ns t isch input setup ti me to clk2x rising edge. [43] 2.5 1.8 ns t ihch input hold time to clk2x rising edge. [43] 0.6 0.6 ns t icsch c]ascaded input setup time to clk2x rising edge. [43] 4.2 3.5 ns t ichch cascaded input hold time to clk2x rising edge. [43] 2.0 2.0 ns t ckhov rising edge of clk2x to lho, fulo, bho, full valid. [44] 8.5 7.0 ns t ckhdv rising edge of clk2x to dq valid. [44] 9.0 7.5 ns t ckhdz rising edge of clk2x to dq high-z. [45] 0.5 8.5 0.5 7.0 ns t ckhsv rising edge of clk2x to sram bus valid. [44] 9.0 7.5 ns t ckhshz rising edge of clk2x to sram bus high-z. [45] 0.5 6.5 0.5 6.0 ns t ckhslz rising edge of clk2x to sram bus low-z. [45] 7.0 6.5 ns table 17-2. ac timing parameters with clk1x parameter description cynse70256-066 cynse70256-083 unit min max min max f clock clk1x frequency. 20 66 20 83 mhz t clok pll lock time. 0.5 0.5 ms t ckhi clk1x high pulse; worst-case duty cycle. [46] 6.75 5.4 ns t cklo clk1x low pulse; worst-case duty cycle. [46] 6.75 5.4 ns t isch input setup time to clk1x edge. [46] 2.5 1.8 ns t ihch input hold time to clk1x edge. [46] 0.6 0.6 ns t icsch cascaded input setup time to clk1x rising edge. [46] 4.2 3.5 ns t ichch cascaded input hold time to clk1x rising edge. [46] 2.0 2.0 ns t ckhov rising edge of clk1x to lho, fulo, bho, full valid. [47] 8.5 7.0 ns t ckhdv rising edge of clk1x to dq valid. [47] 9.0 7.5 ns t ckhdz rising edge of clk1x to dq high-z. [48] 0.5 8.5 0.5 7.0 ns t ckhsv rising edge of clk1x to sram bus valid. [47] 9.0 7.5 ns t ckhshz rising edge of clk1x to sram bus high-z. [48] 0.5 6.5 0.5 6.0 ns t ckhslz rising edge of clk1x to sram bus low-z. [48] 7.0 6.5 ns notes: 43. values are based on 50% signal levels. 44. based on an ac load of c l = 30 pf (see figure 17-1 , figure 17-2 , and figure 17-3 ). 45. these parameters are sampled but not 100% tested, and are based on an ac load of 5 pf. 46. values are based on 50% signal levels and a 50%/50% duty cycle of clk1x. 47. based on an ac load of c l = 30 pf (see figure 17-1 , figure 17-2 , and figure 17-3 ). 48. these parameters are sampled but not 100% tested, and are based on an ac load of 5 pf.
cynse70256 document #: 38-02035 rev. *e page 100 of 109 table 17-3. ac table for t est condition of cynse70256 conditions results input pulse levels (v ddq =3.3v) gnd to 3.3v input pulse levels (v ddq =2.5v) gnd to 2.5v input rise and fall times measured at 0.3v and 2.7v (v ddq =3.3v) 2 ns (see figure 17-1 ) input rise and fall times measured at 0.25v and 2.25v (v ddq =2.5v) 2 ns (see figure 17-1 ) input timing reference levels (v ddq =3.3v) 1.65v input timing reference levels (v ddq =2.5v) 1.25v output reference levels (v ddq =3.3v) 1.65v output reference levels (v ddq =2.5v) 1.25v output load see figure 17-2 and figure 17-3 +3.3v/+2.5v 90% 90% 10% 10% gnd figure 17-1. input wave form for cynse70256 z 0 = 50 ? 50 ? figure 17-2. output load for cynse70256 d out ac load c l v l = 1.65v for v ddq = 3.3v v l = 1.25v for v ddq = 2.5v 208 ? v ddq = 2.5v [49,50] figure 17-3. 2.5 i/o output load equivalent for cynse70256 v ddq q 5 pf 192 ? v ddq = 2.5v for high-z and v ol /v oh n o t es: 49. output loading is specified with cl = 5pf as in figure 17-3 . transition is measured at 200 mv from steady state voltage. 50. the load used for v oh , v ol testing is shown in figure 17-3 .
cynse70256 document #: 38-02035 rev. *e page 101 of 109 clk signal signal signal signal signal group 0 group 2 group 3 group 5 group 4 0 t ihch t isch t icsch t ihch signal group 0: phs_l, rst_l. signal group 1: dq, cmd, cmdv. signal group 2: lhi, bhi, fuli. signal group 3: lho, bho, fulo, full. signal group 4: sadr, ce_l, oe_l, we_l, ale_l, ssf, ssv. signal group 5: dq, ack, eot. t ckhov t ckhov t ckhdz t ckhdv t ckhshz t ckhslz t ckhsv cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle 12 cycle clk2x signal group 1 t ihch t isch t ihch t isch t ichch figure 17-4. ac timing wave forms with clk2x
cynse70256 document #: 38-02035 rev. *e page 102 of 109 clk signal signal signal signal signal group 0 group 2 group 3 group 5 group 4 0 t ihch t isch t icsch t ihch signal group 0: phs_l, rst_l. signal group 1: dq, cmd, cmdv. signal group 2: lhi, bhi, fuli. signal group 3: lho, bho, fulo, full. signal group 4: sadr, ce_l, oe_l, we_l, ale_l, ssf, ssv. signal group 5: dq, ack, eot. t ckhov t ckhov t ckhdz t ckhdv t ckhshz t ckhslz t ckhsv cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 cycle 10 cycle 11 cycle 12 cycle clk1x signal group 1 t isch t ihch t isch t ichch figure 17-5. ac timing wave forms with clk1x
cynse70256 document #: 38-02035 rev. *e page 103 of 109 18.0 pinout descriptions and package diagrams af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1nc v ss rst_l v ss full fulo1 fuli6 v ddq fuli2 fuli0 bho2 v ddq bho0 bhi1 v ddq lho0 lhi6 lhi2 lhi0 id3 id1 id0 trst_l tck tdi v ddq 1 2 v ss v ss v ddq eot ack v ddq fulo0 fuli5 fuli3 v ddq v ss bho1 nc bhi2 bhi0 lho1 lhi4 lhi3 lhi1 id4 id2 v ddq tdo tms v ss dq71 2 3 dq68 dq70 v dd v dd v dd v dd v dd nc2 fuli4 fuli1 v dd v dd v dd v dd v dd v dd lhi5 v ddq nc1 v dd v dd v dd v dd v dd dq69 v ddq 3 4dq66 v ddq v dd v ss v ss v ss v ss v ss v ss v ss v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v dd dq65 dq67 4 5 dq62 dq64 v dd v ss v ss v dd dq61 dq63 5 6 v ddq dq60 v dd v ss v ss v dd dq59 v ddq 6 7 dq56 dq58 v dd v ss v ss v dd dq55 dq57 7 8 dq52 dq54 nc3 v ss v ss nc8 v ddq dq53 8 9 dq48 dq50 v ddq v ss v ss dq49 dq47 dq51 9 10 v ddq dq44 dq46 v ss v ss v ddq dq45 dq43 10 11 dq40 dq42 v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd dq39 dq41 11 12 dq36 dq38 v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd v ddq dq37 12 13 dq34 v ddq v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd dq33 dq35 13 14 dq30 dq32 v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd dq29 dq31 14 15 v ddq dq28 v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd dq27 v ddq 15 16 dq24 dq26 v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd dq23 dq25 16 17 dq22 v ddq dq20 v ss v ss dq19 v ddq dq21 17 18 dq14 dq18 dq16 v ss v ss dq13 dq15 dq17 18 19 v ddq dq12 nc4 v ss v ss nc7 dq11 v ddq 19 20 dq08 dq10 v dd v ss v ss v dd dq07 dq09 20 21 dq04 dq06 v dd v ss v ss v dd v ddq dq05 21 22 dq02 v ddq v dd v ss v ss v dd dq01 dq03 22 23 ssv dq00 v dd v ss v ss v ss v ss v ss v ss v ss v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v dd v ss v ss 23 24 ssf v ddq v dd v dd v dd v dd v dd nc ce_l oe_l v dd v dd v dd v dd v dd v dd sadr13 sadr11 nc6 v dd v dd v dd v dd v dd cfg_l v ddq 24 25 cmd10 v ss cmd8 cmd6 cmd5 cmd3 cmd1 cmdv v ddq phs_l clk_m ode sadr22 sadr21 sadr19 v ddq sadr15 v ddq sadr12 v ddq sadr08 sadr06 sadr05 sadr03 sadr01 v ss high_s peed 25 26 cmd9 v ss cmd7 v ddq cmd4 cmd2 cmd0 ale_l we_l clk1x/ clk2x sadr23 v ddq sadr20sadr18sadr17sadr16sadr14sadr10sadr09sadr07 v ddq sadr04 sadr02 v ddq sadr00 v ddq 26 af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a figure 18-1. pinout diagram table 18-1. pinout descriptions for pinout diagram package ball number signal name signal type package ball number signal name signal type a1 v ddq [51] 2.5v/3.3v aa26 cmd[2] input a10 dq[43] i/o aa3 v dd 1.5v a11 dq[41] i/o aa4 v ss ground a12 dq[37] i/o ab1 full output a13 dq[35] i/o ab2 ack output-t a14 dq[31] i/o ab23 vss ground a15 v ddq 2.5v/3.3v ab24 v dd 1.5v a16 dq[25] i/o ab25 cmd[5] input a17 dq[21] i/o ab26 cmd[4] input a18 dq[17] i/o ab3 v dd 1.5v a19 v ddq 2.5v/3.3v ab4 v ss ground a2 dq[71] i/o ac1 v ss ground a20 dq[09] i/o ac10 v ss ground a21 dq[05] i/o ac11 v dd 1.5v a22 dq[03] i/o ac12 v dd 1.5v a23 v ss ground ac13 v dd 1.5v a24 v ddq 2.5v/3.3v ac14 v dd 1.5v a25 high_speed ground ac15 v dd 1.5v a26 v ddq 2.5v/3.3v ac16 v dd 1.5v note: 51. all v ddq pins should be set to either 2.5v or 3.3v.
cynse70256 document #: 38-02035 rev. *e page 104 of 109 a3 v ddq 2.5v/3.3v ac17 v ss ground a4 dq[67] i/o ac18 v ss ground a5 dq[63] i/o ac19 v ss ground a6 v ddq 2.5v3.3v ac2 eot output-t a7 dq[57] i/o ac20 v ss ground a8 dq[53] i/o ac21 v ss ground a9 dq[51] i/o ac22 v ss ground aa1 fulo[1] output ac23 v ss ground aa2 v ddq 2.5v/3.3v ac24 v dd 1.5v aa23 vss ground ac25 cmd[6] input aa24 v dd 1.5v ac26 v ddq 2.5v/3.3v aa25 cmd[3] input ac3 v dd 1.5v ac4 v ss ground ae10 dq[44] i/o ac5 v ss ground ae11 dq[42] i/o ac6 v ss ground ae12 dq[38] i/o ac7 v ss ground ae13 v ddq 2.5v/3.3v ac8 v ss ground ae14 dq[32] i/o ac9 v ss ground ae15 dq[28] i/o ad1 rst_l input ae16 dq[26] i/o ad10 dq[46] i/o ae17 v ddq 2.5v/3.3v ad11 v dd 1.5v ae18 dq[18] i/o ad12 v dd 1.5v ae19 dq[12] i/o ad13 v dd 1.5v ae2 v ss ground ad14 v dd 1.5v ae20 dq[10] i/o ad15 v dd 1.5v ae21 dq[06] i/o ad16 v dd 1.5v ae22 v ddq 2.5v/3.3v ad17 dq[20] i/o ae23 dq[00] i/o ad18 dq[16] i/o ae24 v ddq 2.5v/3.3v ad19 nc no connect ae25 v ss ground ad2 v ddq 2.5v/3.3v ae26 v ss ground ad20 v dd 1.5v ae3 dq[70] i/o ad21 v dd 1.5v ae4 v ddq 2.5v/3.3v ad22 v dd 1.5v ae5 dq[64] i/o ad23 v dd 1.5v ae6 dq[60] i/o ad24 v dd 1.5v ae7 dq[58] i/o ad25 cmd[8] input ae8 dq[54] i/o ad26 cmd[7] input ae9 dq[50] i/o ad3 v dd 1.5v af1 nc no connect ad4 v dd 1.5v af10 v ddq 2.5v/3.3v ad5 v dd 1.5v af11 dq[40] i/o ad6 v dd 1.5v af12 dq[36] i/o ad7 v dd 1.5v af13 dq[34] i/o ad8 nc no connect af14 dq[30] i/o table 18-1. pinout descriptions for pinout diagram (continued) package ball number signal name signal type package ball number signal name signal type
cynse70256 document #: 38-02035 rev. *e page 105 of 109 ad9 v ddq 2.5v/3.3v af15 v ddq 2.5v/3.3v ae1 v ss ground af16 dq[24] i/o af17 dq[22] i/o b23 v ss ground af18 dq[14] i/o b24 cfg_l input af19 v ddq 2.5v/3.3v b25 v ss ground af2 v ss ground b26 sadr[0] output-t af20 dq[08] i/o b3 dq[69] i/o af21 dq[04] i/o b4 dq[65] i/o af22 dq[02] i/o b5 dq[61] i/o af23 ssv output-t b6 dq[59] i/o af24 ssf output-t b7 dq[55] i/o af25 cmd[10] input b8 v ddq 2.5v/3.3v af26 cmd[9] input b9 dq[47] i/o af3 dq[68] i/o c1 tck input af4 dq[66] i/o c10 v ddq 2.5v/3.3v af5 dq[62] i/o c11 v dd 1.5v af6 v ddq 2.5v/3.3v c12 v dd 1.5v af7 dq[56] i/o c13 v dd 1.5v af8 dq[52] i/o c14 v dd 1.5v af9 dq[48] i/o c15 v dd 1.5v b1 tdi input c16 v dd 1.5v b10 dq[45] i/o c17 dq[19] i/o b11 dq[39] i/o c18 dq[13] i/o b12 v ddq 2.5v/3.3v c19 nc no connect b13 dq[33] i/o c2 tms input b14 dq[29] i/o c20 v dd 1.5v b15 dq[27] i/o c21 v dd 1.5v b16 dq[23] i/o c22 v dd 1.5v b17 v ddq 2.5v/3.3v c23 v dd 1.5v b18 dq[15] i/o c24 v dd 1.5v b19 dq[11] i/o c25 sadr[1] output-t b2 v ss ground c26 v ddq 2.5v/3.3v b20 dq[07] i/o c3 v dd 1.5v b21 v ddq 2.5v/3.3v c4 v dd 1.5v b22 dq[01] i/o c5 v dd 1.5v c6 v dd 1.5v e24 v dd 1.5v c7 v dd 1.5v e25 sadr[5] output-t c8 nc no connect e26 sadr[4] output-t c9 dq[49] i/o e3 v dd 1.5v d1 trst_l input e4 v ss ground d10 vss ground f1 id[1] input d11 v dd 1.5v f2 id[2] input d12 v dd 1.5v f23 v ss ground table 18-1. pinout descriptions for pinout diagram (continued) package ball number signal name signal type package ball number signal name signal type
cynse70256 document #: 38-02035 rev. *e page 106 of 109 d13 v dd 1.5v f24 v dd 1.5v d14 v dd 1.5v f25 sadr[6] output-t d15 v dd 1.5v f26 v ddq 2.5v/3.3v d16 v dd 1.5v f3 v dd 1.5v d17 v ss ground f4 v ss ground d18 v ss ground g1 id[3] input d19 v ss ground g2 id[4] input d2 tdo output-t g23 v ss ground d20 v ss ground g24 v dd 1.5v d21 v ss ground g25 sadr[8] output-t d22 v ss ground g26 sadr[7] output-t d23 v ss ground g3 v dd 1.5v d24 v dd 1.5v g4 v ss ground d25 sadr[3] output-t h1 lhi[0] no connect d26 sadr[2] output-t h2 lhi[1] input d3 v dd 1.5v h23 v ss ground d4 v ss ground h24 nc no connect d5 v ss ground h25 v ddq 2.5v/3.3v d6 v ss ground h26 sadr[9] output-t d7 v ss ground h3 nc no connect d8 v ss ground h4 v ss ground d9 v ss ground j1 lhi[2] input e1 id[0] no connect j2 lhi[3] input e2 v ddq 2.5v/3.3v j23 v ss ground e23 v ss ground j24 sadr[11] output-t j25 sadr[12] output-t m2 bhi[0] input j26 sadr[10] output-t m23 v dd 1.5v j3 v ddq 2.5v/3.3v m24 v dd 1.5v j4 v ss ground m25 v ddq 2.5v/3.3v k1 lhi[6] input m26 sadr[17] output-t k2 lhi[4] input m3 v dd 1.5v k23 v ss ground m4 v dd 1.5v k24 sadr[13] output-t n1 bhi[1] input k25 v ddq 2.5v/3.3v n11 v ss ground k26 sadr[14] output-t n12 v ss ground k3 lhi[5] input n13 v ss ground k4 v ss ground n14 v ss ground l1 lho[0] output n15 v ss ground l11 v ss ground n16 v ss ground l12 v ss ground n2 bhi[2] input l13 v ss ground n23 v dd 1.5v l14 v ss ground n24 v dd 1.5v l15 v ss ground n25 sadr[19] output-t table 18-1. pinout descriptions for pinout diagram (continued) package ball number signal name signal type package ball number signal name signal type
cynse70256 document #: 38-02035 rev. *e page 107 of 109 l16 v ss ground n26 sadr[18] output-t l2 lho[1] output n3 v dd 1.5v l23 v dd 1.5v n4 v dd 1.5v l24 v dd 1.5v p1 bho[0] output l25 sadr[15] output-t p11 v ss ground l26 sadr[16] output-t p12 v ss ground l3 v dd 1.5v p13 v ss ground l4 v dd 1.5v p14 v ss ground m1 v ddq 2.5v/3.3v p15 v ss ground m11 v ss ground p16 v ss ground m12 v ss ground p2 nc no connect m13 v ss ground p23 v dd 1.5v m14 v ss ground p24 v dd 1.5v m15 v ss ground p25 sadr[21] output-t m16 v ss ground p26 sadr[20] output-t p3 v dd 1.5v u24 oe_l output-t p4 v dd 1.5v u25 phs_l input r1 v ddq 2.5v/3.3v u26 clk1x/clk2x input r11 v ss ground u3 fuli[1] input r12 v ss ground u4 v ss ground r13 v ss ground v1 fuli[2] input r14 v ss ground v2 fuli[3] input r15 v ss ground v23 v ss ground r16 v ss ground v24 ce_l output-t r2 bho[1] output v25 v ddq 2.5v/3.3v r23 v dd 1.5v v26 we_l output-t r24 v dd 1.5v v3 fuli[4] input r25 sadr[22] output-t v4 v ss ground r26 v ddq 2.5v/3.3v w1 v ddq 2.5v/3.3v r3 v dd 1.5v w2 fuli[5] input r4 v dd 1.5v w23 v ss ground t1 bho[2] output w24 nc output-t t11 v ss ground w25 cmdv input t12 v ss ground w26 ale_l output-t t13 v ss ground w3 nc no connect t14 v ss ground w4 v ss ground t15 v ss ground y1 fuli[6] input t16 v ss ground y2 fulo[0] output t2 v ss ground y23 v ss ground t23 v dd 1.5v y24 v dd 1.5v t24 v dd 1.5v y25 cmd[1] input t25 clk_mode input y26 cmd[0] input t26 sadr[23] output-t y3 v dd 1.5v table 18-1. pinout descriptions for pinout diagram (continued) package ball number signal name signal type package ball number signal name signal type
cynse70256 document #: 38-02035 rev. *e page 108 of 109 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. 19.0 ordering information 20.0 package diagram associative processing technology ? (apt) is a trademark of cypress semiconduc tor. all product and company names mentioned in this document are the trademarks of their respective holders. t3 v dd 1.5v y4 v ss ground t4 v dd 1.5v u1 fuli[0] no connect u2 v ddq 2.5v/3.3v u23 v ss ground table 19-1. ordering information part number description i/o voltage frequency temperature range cynse70256?066bhc nse 2.5v/3.3v 66 mhz commercial cynse70256?083bhc nse 2.5v/3.3v 83 mhz commercial table 18-1. pinout descriptions for pinout diagram (continued) package ball number signal name signal type package ball number signal name signal type 388-ball hsbga (35 x 35 x 2.33 mm) bh388 51-85102-**
cynse70256 document #: 38-02035 rev. *e page 109 of 109 document history page document title: cynse70256 network search engine document number: 38-02035 rev. ecn no. issue date orig. of change description of change ** 110448 11/29/01 afx new data sheet *a 112905 03/22/02 ed added 3.3v i/o specs. added package diagrams. *b 115995 08/27/02 khs updated ac timing, dc char acteristics, jtag, pinout diagram and pinout description. removed references to test signals from pinout diagram, pinout description and signal description. added power section covering power-up sequence and power consumption. removed all references to 1.8v i/o. removed all references to clk_tune[3:0] and set it to 100% (?1001?). *c 119308 11/22/02 khs changed package from bgc to bhc. added min hold timing to 0.5 ns for t ckhdz and t ckhshz . added note to power-up sequence. updated power-up figures. remove alternative power-up sequence. added note to jtag testing. *d 125508 05/08/03 dcu added note for lhi[0] and fuli[0] being unconnected. added ground in empty pin description. clarified parallel write description. changed diagram for power-up sequence. changed from preliminary to final data sheet *e 131896 12/12/03 fsg minor change: upload mpn to external website. no content change

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